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W989D6KB Schematic ( PDF Datasheet ) - Winbond

Teilenummer W989D6KB
Beschreibung 512Mb Mobile LPSDR
Hersteller Winbond
Logo Winbond Logo 




Gesamt 30 Seiten
W989D6KB Datasheet, Funktion
W989D6KB / W989D2KB
1. GENERAL DESCRIPTION
512Mb Mobile LPSDR
The Winbond 512Mb Low Power SDRAM is a low power synchronous memory containing
536,870,912 memory cells fabricated with Winbond high performance process technology.
It is designed to consume less power than the ordinary SDRAM with low power features essential
for applications which use batteries. It is available in two organizations: 4,194,304-words × 4 banks
× 32 bits or 8,388,608 words × 4 banks × 16 bits. The device operates in a fully synchronous
mode, and the output data are synchronized to positive edges of the system clock and is capable
of delivering data at clock rate up to 166MHz. The device supports special low power functions
such as Partial Array Self Refresh (PASR) and Automatic Temperature Compensated Self Refresh
(ATCSR).
The Low Power SDRAM is suitable for 2.5G / 3G cellular phone, PDA, digital still camera, mobile
game consoles and other handheld applications where large memory density and low power
consumption are required. The device operates from 1.8V power supply, and supports the 1.8V
LVCMOS bus interface.
2. FEATURES
Power supply VDD = 1.7V~1.95V
VDDQ = 1.7V~1.95V
Frequency : 166MHz(-6)
Standard Self Refresh Mode
Programmable Partial Array Self Refresh
Power Down Mode
Deep Power Down Mode (DPD)
Programmable output buffer driver strength
Automatic Temperature Compensated Self Refresh
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Refresh: refresh cycle 64ms
Interface: LVCMOS
Support package :
54 balls VFBGA (x16)
90 balls VFBGA (x32)
Operating Temperature Range
Extended (-25°C ~ +85°C)
Industrial (-40°C ~ +85°C)
-1-
Publication Release Date : October 07, 2013
Revision : A01-003






W989D6KB Datasheet, Funktion
W989D6KB / W989D2KB
5. PIN DESCRIPTION
5.1 Signal Description
Ball Name
Function
512Mb Mobile LPSDR
Description
A [n : 0]
BA0, BA1
Address
Bank Select
Multiplexed pins for row and column address.
A10 is Auto Precharge Select
Select bank to activate during row address latch time, or bank to
read/write during address latch time.
DQ0~DQ15 (×16)
DQ0~DQ31 (×32)
CS
Multiplexed pins for data output and input.
Data Input/ Output
Chip Select
Disable or enable the command decoder. When command decoder is
disabled, new command is ignored and previous operation continues.
RAS
Row
Command input. When sampled at the rising edge of the clock, RAS ,
Address Strobe CAS and WE define the operation to be executed.
CAS
Column
Referred to RAS
Address Strobe
WE
UDQM / LDQM(x16)
DQM0 ~ DQM3 (x32)
Write Enable
I/O Mask
Referred to WE
The output buffer is placed at Hi-Z (with latency of 2 in CL=2, 3;) when
DQM is sampled high in read cycle. In write cycle, sampling DQM high
will block the write operation with zero latency
CLK
CKE
VDD
Clock Inputs
Clock Enable
Power
System clock used to sample inputs on the rising edge of clock.
CKE controls the clock activation and deactivation. When CKE is low,
Power Down mode, Suspend mode or Self Refresh mode is entered.
Power supply for input buffers and logic circuit inside DRAM.
VSS
VDDQ
VSSQ
Ground
Power for I/O
Buffer
Ground for
I/O Buffer
Ground for input buffers and logic circuit inside DRAM.
Power supply separated from VDD, used for output buffers to improve
noise.
Separated ground from VSS, used for output buffers to improve noise.
NC No Connection No connection
-6-
Publication Release Date : October 07, 2013
Revision : A01-003

6 Page









W989D6KB pdf, datenblatt
W989D6KB / W989D2KB
512Mb Mobile LPSDR
7.5 Automatic Temperature Compensated Self Refresh Current Feature
Partial Array Self
Refresh Setting EMR [2:0]
Operating Temperature
Setting EMR[4:3]
EMR[2:0]=000, CKE=0.2V
All 4 banks are Refreshed
85°C
EMR[2:0]=001, CKE=0.2V
Bank 0 and 1 are Refreshed
85°C
Sym Max. Unit
450
IDD6 350 μA
EMR[2:0]=010, CKE=0.2V
Only Bank 0 is Refreshed
85°C
300
Notes:
1. A full initialization sequence is required before proper device operation is ensured.
2. Idd is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and
the outputs open.
3. The Idd current will increase or decrease proportionally according to the amount of frequency alteration for the test
condition.
4. Address transitions average one transition every 2 clocks.
5. Measurement is taken 500ms after entering into this operating mode to provide tester measuring unit settling time.
6. Other input signals can transition only one time for every 2 clocks and are otherwise at valid Vih or Vil levels.
7. CKE is HIGH during the REFRESH command period tRFC (MIN) else CKE is LOW.
8. Typical values at 25°C (not a maximum value).
9. Enables on-die refresh and address counters.
10. Values for Idd6 85°C full array and partial array are guaranteed for the entire temperature range. All other Idd6
values are estimated.
- 12 -
Publication Release Date : October 07, 2013
Revision : A01-003

12 Page





SeitenGesamt 30 Seiten
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