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A7129 Schematic ( PDF Datasheet ) - AMICCOM

Teilenummer A7129
Beschreibung Mini Power FSK/GFSK Sub 1GHz Transceiver
Hersteller AMICCOM
Logo AMICCOM Logo 




Gesamt 30 Seiten
A7129 Datasheet, Funktion
A7129
Mini Power FSK/GFSK Sub 1GHz Transceiver
Document Title
Mini Power 315/433/480/510/868/915MHz FSK/GFSK Transceiver with 2K ~ 250Kbps
Revision History
Rev. No.
0.0
0.1
0.2
0.3
History
Initial issue
Modify description of Ch 12 and Ch 13.
Update specification and A50 application circuit
Update Figure 13.1, PLLII (02h) and Fdev (06h, page0)
formula.
Issue Date
Sep., 2011
Feb., 2012
April, 2012
June, 2012
Remark
Objective
Preliminary
Preliminary
Preliminary
Important Notice:
AMICCOM reserves the right to make changes to its products or to discontinue any integrated circuit product or service
without notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable
for use in life-support applications, devices or systems or other critical applications. Use of AMICCOM products in such
applications is understood to be fully at the risk of the customer.
June, 2012, Version 0.3 (PRELIMINARY)
1 AMICCOM Electronics Corporation






A7129 Datasheet, Funktion
5. RF Chip Block Diagram
A7129
Mini Power FSK/GFSK Sub 1GHz Transceiver
Figure 5.1 System Block Diagram
6. Pin Descriptions
Note: I (input), O(output), G(Ground).
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Symbol
BP_RSSI
GND
RFI
VDD_TX
RFO
VDD_VCO
VCO_P
VCO_N
VT
VDD_PLL
XI
XO
GND
SCS
SCK
SDIO
VDD_D
VDD_D
I/O
I/O
G
I
O
O
I
I
I
O
O
I
O
O
DI
DI
DI/O
O
O
Function Description
I: ADC input.
O: RSSI bypass. Connect to bypass capacitor.
Ground.
RF input. Connect to matching circuit.
TX supply voltage input.
RF output. Connect to matching circuit. (recommend powered by VDD directly).
VCO supply voltage input.
VCO positive pin, connected to external inductor.
VCO negative pin, connected to external inductor.
Charge-pump output. Connect to loop filter.
PLL supply voltage input.
Crystal oscillator input. Connect to tank capacitor.
Crystal oscillator output. Connect to tank capacitor.
Digital ground pin.
SPI chip select input.
SPI clock input.
SPI data IO.
Digital supply voltage output. Connect to bypass capacitor.
Digital supply voltage output. Connect to bypass capacitor.
June, 2012, Version 0.3 (PRELIMINARY)
6 AMICCOM Electronics Corporation

6 Page









A7129 pdf, datenblatt
A7129
Mini Power FSK/GFSK Sub 1GHz Transceiver
ADC
R PWR
0Dh
Pin control
W
RFT2
XEM
RFT1
0Eh
Calibration
W MSCRC VTL2
R FCD4 FCD3
0Fh
Modecontrol
W
R
DFCD
--
VBS
WWSE
Legend: -- = unimplemented
PLLEM
RFT0
VTL1
FCD2
SW T
CCER
TRSM
PRS
VTL0
FCD1
RSSC
RSSC
TREM
SCMDS
VTH2
FCD0
VCC
VCC
-- VBD1 VBD0 ADC7 ADC6 ADC5
WMODE INFS IRQI IRQ1 IRQ0 IRQE
VTH1
DVT1
CCE
FECF
VTH0 MVBS
DVT0
WWSE
CRCF
VBCF
FMT
FMT
MVB2
VB2
FMS
FMS
MVB1
VB1
CER
CER
MVB0
VB0
PLLE
PLLE
ADC4
CKOI
MFBS
FBCF
TRSR
TRSR
ADC3 ADC2 ADC1 ADC0
CKO1 CKO0 CKOE SCKI
MFB3
FB3
TRER
TRER
MFB2
FB2
VBC
VBC
MFB1 MFB0
FB1
FBC
FBC
FB0
ADCM
ADCM
9.2 Control Register Description
9.2.1 System clock (Address: 00h)
Address/Name R/W Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00h
System clock
Reset
W SDR6 SDR5 SDR4 SDR3 SDR2 SDR1 SDR0 GRS GRC4 GRC3 GRC2 GRC1 GRC0 CSC2 CSC1 CSC0
R SDR6 SDR5 SDR4 SDR3 SDR2 SDR1 SDR0 GRS GRC4 GRC3 GRC2 GRC1 GRC0 CSC2 CSC1 CSC0
0000000000 100000
SDR[6:0]: Data Rate Divider.
Data rate = 1 ×
f system
128 SDR[6 : 0] +1
where Fsystem is system clock.
If DMOS (0Ah) = 0, Data rate = 1 ×
f CSCK
(recommended).
128 SDR[6 : 0] + 1
If DMOS (0Ah) = 1, Data rate = 1 ×
f CSCK
64 SDR[6 : 0] +1
GRS: Reference Clock Selection for the internal CLK Generator.
[0]: PLL CLK Gen. = FCGRF x 48, where FCGRF is from below GRC divider
[1]: PLL CLK Gen. = FCGRF x 32
GRC[4:0]: Generation Reference Clock Divider.
GRC [4:0] is the clock divider to generate a PFD clock for the internal CLK Generator.
fCGRF
=
f xtal
GRC[4 : 0] + 1
CSC[2:0]: System Clock Divider setting.
CSC is the clock divider of FMSCK to generate the wanted data clock and IF calibration clock
where FMSCK is either from Xtal itself (CGS = 0) or from the internal CLK Generator (CGS = 1).
f CSCK
=
f MSCK
CSC[2 : 0] +1
FCSCK shall be set appropriately, otherwise, IF Filter calibration will be failure.
Please refer to chapter 12 for details.
9.2.2 PLL I (Address: 01h)
Address/Name R/W Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
01h
PLL I
Reset
W
CHI1 CHI0 CHF1 CHF0 CHIS CHFS IP8 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0
10 000000
CHI[1:0]: Reserved. CHI shall be [00].
CHF[1:0]: charge-pump current setting for fractional-N synthesizer. Recommend CHF = [01].
[00]: 48uA
[01]: 96uA
[10]: 192uA
[11]: 384uA
June, 2012, Version 0.3 (PRELIMINARY)
12 AMICCOM Electronics Corporation

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