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PDF PCS3P73Z01AW Data sheet ( Hoja de datos )
| Número de pieza | PCS3P73Z01AW | |
| Descripción | Peak EMI reduction IC | |
| Fabricantes | PulseCore | |
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May 2008
rev 0.3
PCS3P73Z01AW
Wide Frequency range Timing-Safe™ Peak EMI reduction IC
General Features
• 1x , LVCMOS Timing-Safe™ Peak EMI Reduction
• Input frequency:
2MHz - 16MHz @ 2.5V
2MHz - 20MHz @ 3.3V
• Output frequency ( Timing-Safe™):
2MHz - 16MHz @ 2.5V
2MHz - 20MHz @ 3.3V
• Analog Spread Selection up to ±1.5%
• External Input-Output Delay Control option
• Power Down option for Power Save mode
• Supply Voltage: 2.5V±0.2V
3.3V ± 0.3V
• Commercial temperature range
• 8 pin, TSSOP, and TDFN(2X2) COL packages
• The First True Drop-in Solution
Functional Description
PCS3P73Z01AW is a 2.5V/3.3V versatile EMI reduction IC
based on PulseCore Semiconductor’s patent pending
Timing-Safe™ technology. PCS3P73Z01AW accepts one
input from an external reference, and locks on to it
delivering a 1x Timing-Safe™ clock. PCS3wPw73wZ.0D1aAtaWShheaest4U.com
a Frequency Selection (FS) control that facilitates selecting
one of the two frequency ranges within the operating
frequency range. Refer to the frequency Selection table for
details. The device has an SSEXTR pin to select different
deviation and associated Input-Output Skew (TSKEW),
depending upon the value of an external resistor connected
between SSEXTR and GND. PCS3P73Z01AW has a
DLY_CTRL for adjusting the Input-Output clock delay,
depending upon the value of capacitor connected at this
pin to GND. PD#/OE provides the Power Down option.
Outputs will be tri-stated when power down is active.
PCS3P73Z01AW operates from a 2.5V/3.3V supply and is
available in an 8 Pin TSSOP, and TDFN (2X2) COL
Packages, over Commercial temperature range.
Application
PCS3P73Z01AW is targeted for use in Displays, Camera
modules and SDRAM memory interface systems.
Block Diagram
DLY_CTRL VDD
SSEXTR
CLKIN
PLL
PD#/OE
GND
FS
ModOUT
(Timing-Safe™)
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
1 page  
May 2008
rev 0.3
Switching Waveforms
Duty Cycle Timing
OUTPUT
VDD/2
t1
t2
VDD/2
All Outputs Rise/Fall Time
OUTPUT
80%
20%
t3
Input - Output Propagation Delay
80%
20%
t4
INPUT
OUTPUT
VDD/2
VDD/2
t6
VDD/2
PCS3P73Z01AW
www.DataSheet4U.com
3.3V
0V
Input-Output Skew
Timing-Safe™
Input
Output
TSKEW -
TSKEW+
One clock cycle
N=1
TSKEW represents input-output skew
when spread spectrum is ON
For example, TSKEW = ± 0.20 for an Input
clock of 12MHz, translates in to
(1/12MHz) * 0.20=16.66nS
Note: Tskew is measured in units of Clock Period
Wide Frequency range Timing-Safe™ Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
5 of 13
5 Page 
May 2008
rev 0.3
TDFN COL 2x2 8L package Outline drawing
PCS3P73Z01AW
www.DataSheet4U.com
Symbol
A
A3
b
D
E
e
L
Dimensions
Inches
Millimeters
Min
Max
Min
Max
0.027
0.0315
0.70
0.80
0.008 BSC
0.203 BSC
0.008
0.012
0.20
0.30
0.079 BSC
2.00 BSC
0.078 BSC
2.00 BSC
0.020 BSC
0.50 BSC
0.020
0.024
0.50
0.60
Wide Frequency range Timing-Safe™ Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
11 of 13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet PCS3P73Z01AW.PDF ] | |
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