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PCF8574A Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCF8574A
Beschreibung Remote 8-bit I/O expander for I2C-bus
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
PCF8574A Datasheet, Funktion
PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Rev. 5 — 27 May 2013
Product data sheet
1. General description
The PCF8574/74A provides general-purpose remote I/O expansion via the two-wire
bidirectional I2C-bus (serial clock (SCL), serial data (SDA)).
The devices consist of eight quasi-bidirectional ports, 100 kHz I2C-bus interface, three
hardware address inputs and interrupt output operating between 2.5 V and 6 V. The
quasi-bidirectional port can be independently assigned as an input to monitor interrupt
status or keypads, or as an output to activate indicator devices such as LEDs. System
master can read from the input port or write to the output port through a single register.
The low current consumption of 2.5 A (typical, static) is great for mobile applications and
the latched output ports directly drive LEDs.
The PCF8574 and PCF8574A are identical, except for the different fixed portion of the
slave address. The three hardware address pins allow eight of each device to be on the
same I2C-bus, so there can be up to 16 of these I/O expanders PCF8574/74A together on
the same I2C-bus, supporting up to 128 I/Os (for example, 128 LEDs).
The active LOW open-drain interrupt output (INT) can be connected to the interrupt logic
of the microcontroller and is activated when any input state differs from its corresponding
input port register state. It is used to indicate to the microcontroller that an input state has
changed and the device needs to be interrogated without the microcontroller continuously
polling the input register via the I2C-bus.
The internal Power-On Reset (POR) initializes the I/Os as inputs with a weak internal
pull-up 100 A current source.
2. Features and benefits
I2C-bus to parallel port expander
100 kHz I2C-bus interface (Standard-mode I2C-bus)
Operating supply voltage 2.5 V to 6 V with non-overvoltage tolerant I/O held to VDD
with 100 A current source
8-bit remote I/O pins that default to inputs at power-up
Latched outputs directly drive LEDs
Total package sink capability of 80 mA
Active LOW open-drain interrupt output
Eight programmable slave addresses using three address pins
Low standby current (2.5 A typical)
40 C to +85 C operation
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101






PCF8574A Datasheet, Funktion
NXP Semiconductors
PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Table 5. PCF8574A address map
Pin connectivity
Address of PCF8574A
Address byte value
7-bit
A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W Write
Read hexadecimal
address
without R/W
VSS VSS VSS 0 1 1 1 0 0 0 -
70h
71h
38h
VSS VSS VDD 0 1 1 1 0 0 1 -
72h
73h
39h
VSS VDD VSS 0 1 1 1 0 1 0 -
74h
75h
3Ah
VSS VDD VDD 0 1 1 1 0 1 1 -
76h
77h
3Bh
VDD VSS VSS 0 1 1 1 1 0 0
VDD VSS VDD 0 1 1 1 1 0 1
-
-
78h
7Ah
79h
7Bh
3Ch
3Dh
VDD VDD VSS 0 1 1 1 1 1 0 -
7Ch
7Dh
3Eh
VDD VDD VDD 0 1 1 1 1 1 1 -
7Eh
7Fh
3Fh
8. I/O programming
8.1 Quasi-bidirectional I/Os
A quasi-bidirectional I/O is an input or output port without using a direction control register.
Whenever the master reads the register, the value returned to master depends on the
actual voltage or status of the pin. At power on, all the ports are HIGH with a weak 100 A
internal pull-up to VDD, but can be driven LOW by an internal transistor, or an external
signal. The I/O ports are entirely independent of each other, but each I/O octal is
controlled by the same read or write data byte.
Advantages of the quasi-bidirectional I/O over totem pole I/O include:
Better for driving LEDs since the p-channel (transistor to VDD) is small, which saves
die size and therefore cost. LED drive only requires an internal transistor to ground,
while the LED is connected to VDD through a current-limiting resistor. Totem pole I/O
have both n-channel and p-channel transistors, which allow solid HIGH and LOW
output levels without a pull-up resistor — good for logic levels.
Simpler architecture — only a single register and the I/O can be both input and output
at the same time. Totem pole I/O have a direction register that specifies the port pin
direction and it is always in that configuration unless the direction is explicitly
changed.
Does not require a command byte. The simplicity of one register (no need for the
pointer register or, technically, the command byte) is an advantage in some
embedded systems where every byte counts because of memory or bandwidth
limitations.
PCF8574_PCF8574A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 May 2013
© NXP B.V. 2013. All rights reserved.
6 of 33

6 Page









PCF8574A pdf, datenblatt
NXP Semiconductors
PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
I2C-BUS
MULTIPLEXER
SLAVE
Fig 13. System configuration
002aaa966
9.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit (see Figure 14). The acknowledge bit is an active LOW level (generated
by the receiving device) that indicates to the transmitter that the data transfer was
successful.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that wants to issue an
acknowledge bit has to pull down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during the HIGH period of the acknowledge bit related
clock pulse; set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
data output
by transmitter
data output
by receiver
SCL from master
S
START
condition
1
Fig 14. Acknowledgement on the I2C-bus
2
not acknowledge
acknowledge
89
clock pulse for
acknowledgement
002aaa987
PCF8574_PCF8574A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 May 2013
© NXP B.V. 2013. All rights reserved.
12 of 33

12 Page





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