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GS2971A Schematic ( PDF Datasheet ) - Semtech

Teilenummer GS2971A
Beschreibung HD SD SDI Receiver
Hersteller Semtech
Logo Semtech Logo 




Gesamt 30 Seiten
GS2971A Datasheet, Funktion
GS2971A
3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete
with SMPTE Audio and Video Processing
Key Features
• Operation at 2.97Gb/s, 2.97/1.001Gb/s, 1.485Gb/s,
1.485/1.001Gb/s and 270Mb/s
• Supports SMPTE 425M (Level A and Level B), SMPTE
424M, SMPTE 292M, SMPTE 259M-C and DVB-ASI
• Integrated adaptive cable equalizer
• Typical equalized length of Belden 1694A cable:
Š 150m at 2.97Gb/s
Š 250m at 1.485Gb/s
Š 480m at 270Mb/s
• Integrated Reclocker with low phase noise, integrated
VCO
• Serial digital reclocked, or non-reclocked output
• Integrated audio de-embedder for 8 channels of 48kHz
audio
• Integrated audio clock generator
• Ancillary data extraction
• Optional conversion from SMPTE 425M Level B to
Level A for 1080p 50/60 4:2:2 10-bit
• Parallel data bus selectable as either 20-bit or 10-bit
• Comprehensive error detection and correction
features
• Output H, V, F or CEA 861 Timing Signals
• 1.2V digital core power supply, 1.2V and 3.3V analog
power supplies, and selectable 1.8V or 3.3V I/O power
supply
• GSPI Host Interface
• -20ºC to +85ºC operating temperature range
• Low power operation (typically 545mW)
• Small 11mm x 11mm 100-ball BGA package
• Pb-free and RoHS compliant
Applications
Application: Single Link (3G-SDI)
to Dual Link (HD-SDI) Converter
3G-SDI
GS2971A
10-bit
HV F/PCLK
GS2962/72
HV F/PCLK
10-bit
GS2962/72
HD-SDI
Link A
HD-SDI
Link B
3G-SDI
Application: 1080p50/60 Monitor
AES - OUT
GS2971A
AUDIO 1/2
AUDIO 3/4
AUDIO 5/6
AUDIO 7/8
Audio Clocks
Audio
Selector
10-bit
HV F/PCLK
Video
Processor
C TR L/TIMECODE
DAC
Speakers
DAC
Display
Application: Multi-format Downconverter
10-bit bit SD Bypass
Memory
SD/HD/3G-SDI
GS2971A
10-bit
HV F/PCLK
Video
Downconverter &
Aspect Ratio
Conversion
Analog
Sync
Sync
Seperator
AE S 1/2
AE S 3/4
AE S 5/6
AE S 7/8
Audio
Processing
& Delay
GS4901
Audio Clocks
HV F/PCLK
AE S 1/2
AE S 3/4
AE S 5/6
AE S 7/8
10-bit
HD/SD
Serializer
(GS1582,
GS1672)
SD-SDI
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
www.semtech.com
1 of 152






GS2971A Datasheet, Funktion
7. Package & Ordering Information ........................................................................................................ 149
7.1 Package Dimensions ................................................................................................................... 149
7.2 Packaging Data ............................................................................................................................. 150
7.3 Marking Diagram ......................................................................................................................... 150
7.4 Solder Reflow Profiles ................................................................................................................ 151
7.5 Ordering Information ................................................................................................................. 151
Revision History ............................................................................................................................................ 151
List of Figures
Figure 3-1: Digital Input Pin with Schmitt Trigger .............................................................................. 26
Figure 3-2: Bidirectional Digital Input/Output Pin.............................................................................. 26
Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive strength......... 27
Figure 3-4: XTAL1/XTAL2/XTAL-OUT ................................................................................................... 27
Figure 3-5: VBG .............................................................................................................................................. 27
Figure 3-6: LB_CONT .................................................................................................................................... 28
Figure 3-7: Loop Filter .................................................................................................................................. 28
Figure 3-8: SDO/SDO .................................................................................................................................... 28
Figure 3-9: Equalizer Input Equivalent Circuit .................................................................................... 28
Figure 4-1: Level A Mapping ...................................................................................................................... 30
Figure 4-2: Level B Mapping ...................................................................................................................... 30
Figure 4-3: GS2971A Integrated EQ Block Diagram .......................................................................... 32
Figure 4-4: 27MHz Clock Sources ............................................................................................................ 34
Figure 4-5: PCLK to Data and Control Signal Output Timing - SDR Mode 1 .............................. 37
Figure 4-6: PCLK to Data and Control Signal Output Timing - SDR Mode 2 .............................. 38
Figure 4-7: PCLK to Data and Control Signal Output Timing - DDR Mode ................................. 39
Figure 4-8: DDR Video Interface - 3G Level A ..................................................................................... 42
Figure 4-9: DDR Video Interface - 3G Level B ...................................................................................... 43
Figure 4-10: Delay Adjustment Ranges .................................................................................................. 44
Figure 4-11: Switch Line Locking on a Non-Standard Switch Line ............................................... 45
Figure 4-12: H:V:F Output Timing - 3G Level A and HDTV 20-bit Mode .................................... 50
Figure 4-13: H:V:F Output Timing - 3G Level A and HDTV 10-bit Mode
3G Level B 20-bit Mode, each 10-bit stream ......................................................................................... 50
Figure 4-14: H:V:F Output Timing - 3G Level B 10-bit Mode .......................................................... 51
Figure 4-15: H:V:F Output Timing - HD 20-bit Output Mode ......................................................... 51
Figure 4-16: H:V:F Output Timing - HD 10-bit Output Mode ......................................................... 51
Figure 4-17: H:V:F Output Timing - SD 20-bit Output Mode .......................................................... 51
Figure 4-18: H:V:F Output Timing - SD 10-bit Output Mode .......................................................... 51
Figure 4-19: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4) ................................... 53
Figure 4-20: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5) ................................. 54
Figure 4-21: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7) .................... 55
Figure 4-22: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19) ............................................. 55
Figure 4-23: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20) ........................................... 56
Figure 4-24: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22) ........................... 57
Figure 4-25: H:V:DE Output Timing 1920 x 1080p @ 59.94/60 (Format 16) .............................. 57
Figure 4-26: H:V:DE Output Timing 1920 x 1080p @ 50 (Format 31) .......................................... 58
Figure 4-27: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32) .............................. 58
Figure 4-28: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33) .......................................... 59
Figure 4-29: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34) .............................. 59
Figure 4-30: 2K Feature Enhancement ................................................................................................... 63
Figure 4-31: Y/1ANC and C/2ANC Signal Timing .............................................................................. 70
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
6 of 152

6 Page









GS2971A pdf, datenblatt
Table 1-1:Pin Descriptions (Continued)
Pin
Number
C7
D4, E4, F4
D5, E5, F5,
G4, G5
D6, E6, F6,
G6
D7
D8
E1
E2
E7
Name
Timing
Type
Description
RESET_TRST
PLL_GND
CORE_GND
CORE_VDD
SW_EN
JTAG/HOST
EQ_VDD
EQ_GND
SDOUT_TDO
Input
Input Power
Input Power
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to reset the internal operating conditions to default settings
and to reset the JTAG sequence.
Normal mode (JTAG/HOST = LOW):
When LOW, all functional blocks are set to default conditions and
all digital output signals become high impedance.
When HIGH, normal operation of the device resumes.
JTAG test mode (JTAG/HOST = HIGH):
When LOW, all functional blocks are set to default and the JTAG test
sequence is reset.
When HIGH, normal operation of the JTAG test sequence resumes
after RESET_TRST is de-asserted.
GND pins for the Reclocker PLL. Connect to analog GND.
GND connection for device core. Connect to digital GND.
Input Power POWER connection for device core. Connect to 1.2V DC digital.
Input
Input
Input Power
Input Power
Output
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to enable switch-line locking, as described in Section 4.10.1.
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to select JTAG test mode or host interface mode.
When JTAG/HOST is HIGH, the host interface port is configured for
JTAG test.
When JTAG/HOST is LOW, normal operation of the host interface
port resumes.
POWER pin for SDI buffer. Connect to 3.3V DC analog.
GND pin for SDI buffer. Connect to analog GND.
COMMUNICATION SIGNAL OUTPUT
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
GSPI serial data output/test data out.
In JTAG mode (JTAG/HOST = HIGH), this pin is used to shift test
results from the device.
In host interface mode, this pin is used to read status and
configuration data from the device.
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
12 of 152

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