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PDF GS2961A Data sheet ( Hoja de datos )

Número de pieza GS2961A
Descripción HD SD SDI Receiver
Fabricantes Semtech　
Logotipo Semtech Logotipo



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GS2961A
3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete
with SMPTE Video Processing
Key Features
• Operation at 2.97Gb/s, 2.97/1.001Gb/s, 1.485Gb/s,
1.485/1.001Gb/s and 270Mb/s
• Supports SMPTE 425M (Level A and Level B), SMPTE
424M, SMPTE 292M, SMPTE 259M-C and DVB-ASI
• Integrated adaptive cable equalizer
• Typical equalized length of Belden 1694A cable:
Š 150m at 2.97Gb/s
Š 250m at 1.485Gb/s
Š 480m at 270Mb/s
• Integrated Reclocker with low phase noise, integrated
VCO
• Serial digital reclocked, or non-reclocked output
• Ancillary data extraction
• Optional conversion from SMPTE 425M Level B to
Level A for 1080p 50/60 4:2:2 10-bit
• Parallel data bus selectable as either 20-bit or 10-bit
• Comprehensive error detection and correction
features
• Output H, V, F or CEA 861 Timing Signals
• 1.2V digital core power supply, 1.2V and 3.3V analog
power supplies, and selectable 1.8V or 3.3V I/O power
supply
• GSPI Host Interface
• Wide temperature range of -40ºC to +85ºC
• Low power operation (typically 515mW)
• Small 11mm x 11mm 100-ball BGA package
• Pb-free and ROHS compliant
Applications
Application: Single Link (3G-SDI)
to Dual Link (HD-SDI) Converter
3G-SDI
GS2961A
10-bit
HV F/PCLK
HV F/PCLK
10-bit
GS2962
GS2962
HD-SDI
Link A
HD-SDI
Link B
HD-SDI
Link A
HD-SDI
Link B
Application: Dual Link (HD-SDI)
to Single Link (3G-SDI) Converter
HD-SDI
Deserializer
GS2961A
10-bit
HV F/PCLK
FIFO
WR
HD-SDI
Deserializer
GS2961A
10-bit
HV F/PCLK
FIFO
WR
10-bit
HV F/PCLK
10-bit
GS2962
3G-SDI
GS4910
HVF
X TAL
Description
The GS2961A is a multi-rate SDI integrated Receiver which
includes complete SMPTE processing, as per SMPTE 425M,
292M and SMPTE 259M-C. The SMPTE processing features
can be bypassed to support signals with other coding
schemes.
The GS2961A integrates Gennum's adaptive cable
equalizer technology, achieving unprecedented cable
lengths and jitter tolerance. It features DC restoration to
compensate for the DC content of SMPTE pathological
signals.
The device features an Integrated Reclocker with an
internal VCO and a wide Input Jitter Tolerance (IJT) of
0.7UI.
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
www.semtech.com
1 of 104

1 page




GS2961A pdf
List of Figures
Figure 3-1: Digital Input Pin with Schmitt Trigger............................................................................... 22
Figure 3-2: Bidirectional Digital Input/Output Pin.............................................................................. 22
Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive strength ........ 23
Figure 3-4: XTAL1/XTAL2/XTAL-OUT ................................................................................................... 23
Figure 3-5: VBG .............................................................................................................................................. 24
Figure 3-6: LB_CONT .................................................................................................................................... 24
Figure 3-7: Loop Filter .................................................................................................................................. 24
Figure 3-8: SDO/SDO .................................................................................................................................... 25
Figure 3-9: Equalizer Input Equivalent Circuit .................................................................................... 25
Figure 4-1: Level A Mapping ...................................................................................................................... 27
Figure 4-2: Level B Mapping ...................................................................................................................... 27
Figure 4-3: GS2961A Integrated EQ Block Diagram .......................................................................... 28
Figure 4-4: 27MHz Clock Sources ............................................................................................................ 31
Figure 4-5: PCLK to Data and Control Signal Output Timing - SDR Mode 1 .............................. 34
Figure 4-6: PCLK to Data and Control Signal Output Timing - SDR Mode 2 .............................. 35
Figure 4-7: PCLK to Data and Control Signal Output Timing - DDR Mode ................................. 36
Figure 4-8: DDR Video Interface - 3G Level A ..................................................................................... 39
Figure 4-9: DDR Video Interface - 3G Level B ...................................................................................... 40
Figure 4-10: Delay Adjustment Ranges .................................................................................................. 41
Figure 4-11: Switch Line Locking on a Non-Standard Switch Line ............................................... 42
Figure 4-12: H:V:F Output Timing - 3G Level A and HDTV 20-bit Mode .................................... 46
Figure 4-13: H:V:F Output Timing - 3G Level A and HDTV 10-bit Mode
3G Level B 20-bit Mode, each 10-bit stream ......................................................................................... 47
Figure 4-14: H:V:F Output Timing - 3G Level B 10-bit Mode .......................................................... 47
Figure 4-15: H:V:F Output Timing - HD 20-bit Output Mode ......................................................... 47
Figure 4-16: H:V:F Output Timing - HD 10-bit Output Mode ......................................................... 47
Figure 4-17: H:V:F Output Timing - SD 20-bit Output Mode .......................................................... 47
Figure 4-18: H:V:F Output Timing - SD 10-bit Output Mode .......................................................... 47
Figure 4-19: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4) ................................... 49
Figure 4-20: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5) ................................. 50
Figure 4-21: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7) .................... 51
Figure 4-22: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19) ............................................. 51
Figure 4-23: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20) ........................................... 52
Figure 4-24: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22) ........................... 53
Figure 4-25: H:V:DE Output Timing 1920 x 1080p @ 59.94/60 (Format 16) .............................. 53
Figure 4-26: H:V:DE Output Timing 1920 x 1080p @ 50 (Format 31) .......................................... 54
Figure 4-27: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32) .............................. 54
Figure 4-28: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33) .......................................... 55
Figure 4-29: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34) .............................. 55
Figure 4-30: 2K Feature Enhancement ................................................................................................... 59
Figure 4-31: Y/1ANC and C/2ANC Signal Timing .............................................................................. 66
Figure 4-32: Ancillary Data Extraction - Step A .................................................................................. 73
Figure 4-33: Ancillary Data Extraction - Step B ................................................................................... 74
Figure 4-34: Ancillary Data Extraction - Step C .................................................................................. 74
Figure 4-35: Ancillary Data Extraction - Step D .................................................................................. 75
Figure 4-36: GSPI Application Interface Connection ........................................................................ 77
Figure 4-37: Command Word Format ..................................................................................................... 78
Figure 4-38: Data Word Format ................................................................................................................ 78
Figure 4-39: Write Mode .............................................................................................................................. 79
Figure 4-40: Read Mode ............................................................................................................................... 79
Figure 4-41: GSPI Time Delay .................................................................................................................... 79
Figure 4-42: In-Circuit JTAG ...................................................................................................................... 95
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
5 of 104

5 Page





GS2961A arduino
Table 1-1: Pin Descriptions (Continued)
Pin
Number
E8
Name
SDIN_TDI
Timing
Type
Input
F1, G1
F7
AGCP, AGCN
CS_TMS
Input
F8 SCLK_TCK
Input
F9, F10, H9,
H10, J8, J9,
J10, K8, K9,
K10
DOUT8, 9, 6, 7, 1,
4, 5, 0, 2, 3
Output
Description
COMMUNICATION SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
GSPI serial data in/test data in.
In JTAG mode (JTAG/HOST = HIGH), this pin is used to shift test data
into the device.
In host interface mode, this pin is used to write address and
configuration data words into the device.
Automatic Gain Control for the equalizer. Attach the AGC capacitor
between these pins.
COMMUNICATION SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Chip select / test mode start.
In JTAG mode (JTAG/HOST = HIGH), this pin is Test Mode Start, used
to control the operation of the JTAG test.
In host interface mode (JTAG/HOST = LOW), this pin operates as the
host interface chip select and is active LOW.
COMMUNICATION SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Serial data clock signal.
In JTAG mode (JTAG/HOST = HIGH), this pin is the JTAG clock.
In host interface mode (JTAG/HOST = LOW), this pin is the host
interface serial bit clock.
All JTAG/host interface addresses and data are shifted into/out of
the device synchronously with this clock.
PARALLEL DATA BUS
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
20-bit mode
20bit/10bit = HIGH
SMPTE mode (SMPTE_BYPASS = HIGH
and DVB_ASI = LOW):
Chroma data output for SD and HD
data rates; Data Stream 2 for 3G data
rate
DVB-ASI mode (SMPTE_BYPASS = LOW
and DVB_ASI = HIGH):
Not defined
Data-Through mode (SMPTE_BYPASS =
LOW and DVB_ASI = LOW):
Data output
10-bit mode
20bit/10bit = LOW
Forced LOW
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
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