GS2960A Datasheet PDF - Semtech
| Part Number | GS2960A | |
| Description | HD SD SDI Receiver | |
| Manufacturers | Semtech | |
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GS2960A
3Gb/s, HD, SD SDI Receiver Complete with SMPTE Video Processing
Key Features
• Operation at 2.97Gb/s, 2.97/1.001Gb/s, 1.485Gb/s,
1.485/1.001Gb/s and 270Mb/s
• Supports SMPTE 425M (Level A and Level B), SMPTE
424M, SMPTE 292, SMPTE 259M-C and DVB-ASI
• Integrated Reclocker
• Integrated low phase noise VCO
• Serial digital reclocked, or non-reclocked loop-through
output
• Ancillary data extraction
• Optional conversion from SMPTE 425M Level B to
Level A for 1080p 50/60 4:2:2 10-bit inputs
• Parallel data bus selectable as either 20-bit or 10-bit
• Comprehensive error detection and correction
features
• Output H, V, F or CEA 861 Timing Signals
• 1.2V digital core power supply, 1.2V and 3.3V analog
power supplies, and selectable 1.8V or 3.3V I/O power
supply
• GSPI Host Interface
• Wide temperature range of -40ºC to +85ºC
• Low power operation (typically 350 mW)
• Small 11mm x 11mm 100-ball BGA package
• Pb-free and RoHS compliant
Applications
Application: Single Link (3G-SDI)
to Dual Link (HD-SDI) Converter
3G-SDI
Gennum
Equalizer
GS2960A
10-bit
HV F/PCLK
HV F/PCLK
10-bit
GS2962
GS2962
HD-SDI
Link A
HD-SDI
Link B
HD-SDI
Link A
HD-SDI
Link B
Application: Dual Link (HD-SDI)
to Single Link (3G-SDI) Converter
HD-SDI
Deserializer
GS2960A
10-bit
HV F/PCLK
FIFO
WR
HD-SDI
Deserializer
GS2960A
10-bit
HV F/PCLK
FIFO
WR
10-bit
HV F/PCLK
10-bit
GS2962
3G-SDI
GS4910
HVF
X TAL
Description
The GS2960A is a multi-rate SDI Receiver which includes
complete SMPTE processing, as per SMPTE 425M, 292 and
SMPTE 259M-C. The SMPTE processing features can be
bypassed to support signals with other coding schemes.
The device features an integrated Reclocker with an
internal VCO and a wide Input Jitter Tolerance (IJT) of
0.7UI.
A serial digital loop through output is provided, which can
be configured to output either reclocked or non-reclocked
serial digital data. The Serial Digital Output can be
connected to an external Cable Driver.
The device operates in one of four basic modes: SMPTE
mode, DVB-ASI mode, Data-Through mode or Standby
mode.
In SMPTE mode, the GS2960A performs SMPTE
de-scrambling and NRZI to NRZ decoding and word
alignment. Line-based CRC errors, line number errors, TRS
errors and ancillary data check sum errors can all be
detected. The GS2960A also provides ancillary data
extraction. The entire ancillary data packet is extracted,
and written to host-accessible registers. Other processing
functions include H:V:F timing extraction, Luma and
Chroma ancillary data indication, video standard
detection, and SMPTE 352M packet detection and
decoding. All of the processing features are optional and
may be enabled or disabled via the Host Interface.
GS2960A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54384 - 2
September 2012
www.semtech.com
1 of 99
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List of Figures
Figure 3-1: Digital Input Pin with Schmitt Trigger............................................................................... 22
Figure 3-2: Bidirectional Digital Input/Output Pin.............................................................................. 22
Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive strength......... 23
Figure 3-4: XTAL1/XTAL2/XTAL-OUT ................................................................................................... 23
Figure 3-5: VBG .............................................................................................................................................. 23
Figure 3-6: LB_CONT .................................................................................................................................... 24
Figure 3-7: Loop Filter .................................................................................................................................. 24
Figure 3-8: SDI/SDI and TERM .................................................................................................................. 24
Figure 3-9: SDO/SDO .................................................................................................................................... 24
Figure 4-1: Level A Mapping ...................................................................................................................... 25
Figure 4-2: Level B Mapping ...................................................................................................................... 26
Figure 4-3: 27MHz Clock Sources ............................................................................................................ 29
Figure 4-4: PCLK to Data and Control Signal Output Timing - SDR Mode 1 .............................. 32
Figure 4-5: PCLK to Data and Control Signal Output Timing - SDR Mode 2 .............................. 33
Figure 4-6: PCLK to Data and Control Signal Output Timing - DDR Mode ................................. 34
Figure 4-7: DDR Video Interface - 3G Level A ..................................................................................... 37
Figure 4-8: DDR Video Interface - 3G Level B ...................................................................................... 38
Figure 4-9: Delay Adjustment Ranges .................................................................................................... 39
Figure 4-10: Switch Line Locking on a Non-Standard Switch Line ............................................... 40
Figure 4-11: H:V:F Output Timing - 3G Level A and HDTV 20-bit Mode .................................... 44
Figure 4-12: H:V:F Output Timing - 3G Level A and HDTV 10-bit Mode
3G Level B 20-bit Mode, each 10-bit stream ......................................................................................... 44
Figure 4-13: H:V:F Output Timing - 3G Level B 10-bit Mode .......................................................... 45
Figure 4-14: H:V:F Output Timing - HD 20-bit Output Mode ......................................................... 45
Figure 4-15: H:V:F Output Timing - HD 10-bit Output Mode ......................................................... 45
Figure 4-16: H:V:F Output Timing - SD 20-bit Output Mode .......................................................... 45
Figure 4-17: H:V:F Output Timing - SD 10-bit Output Mode .......................................................... 45
Figure 4-18: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4) ................................... 47
Figure 4-19: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5) ................................. 47
Figure 4-20: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7) .................... 48
Figure 4-21: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19) ............................................. 48
Figure 4-22: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20) ........................................... 49
Figure 4-23: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22) ........................... 50
Figure 4-24: H:V:DE Output Timing 1920 x 1080p @ 59.94/60 (Format 16) .............................. 50
Figure 4-25: H:V:DE Output Timing 1920 x 1080p @ 50 (Format 31) .......................................... 51
Figure 4-26: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32) .............................. 51
Figure 4-27: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33) .......................................... 52
Figure 4-28: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34) .............................. 52
Figure 4-29: 2K Feature Enhancement ................................................................................................... 56
Figure 4-30: Y/1ANC and C/2ANC Signal Timing .............................................................................. 63
Figure 4-31: Ancillary Data Extraction - Step A .................................................................................. 70
Figure 4-32: Ancillary Data Extraction - Step B ................................................................................... 71
Figure 4-33: Ancillary Data Extraction - Step C .................................................................................. 71
Figure 4-34: Ancillary Data Extraction - Step D .................................................................................. 72
Figure 4-35: GSPI Application Interface Connection ........................................................................ 74
Figure 4-36: Command Word Format ..................................................................................................... 75
Figure 4-37: Data Word Format ................................................................................................................ 76
Figure 4-38: Write Mode .............................................................................................................................. 76
Figure 4-39: Read Mode ............................................................................................................................... 76
Figure 4-40: GSPI Time Delay .................................................................................................................... 76
Figure 4-41: In-Circuit JTAG ...................................................................................................................... 92
Figure 4-42: System JTAG ........................................................................................................................... 92
Figure 4-43: Reset Pulse ............................................................................................................................... 93
Figure 7-1: Pb-free Solder Reflow Profile .............................................................................................. 98
GS2960A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54384 - 2
September 2012
5 of 99
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ GS2960A.PDF Datasheet ] | |
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