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GS1671A Schematic ( PDF Datasheet ) - Semtech

Teilenummer GS1671A
Beschreibung HD/SD SDI Receiver
Hersteller Semtech
Logo Semtech Logo 




Gesamt 30 Seiten
GS1671A Datasheet, Funktion
GS1671A
HD/SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with
SMPTE Audio and Video Processing
Key Features
• Operation at 1.485Gb/s, 1.485/1.001Gb/s and 270Mb/s
• Supports SMPTE 292M, SMPTE 259M-C and DVB-ASI
• Integrated adaptive cable equalizer
• Typical equalized length of Belden 1694A cable:
Š 230m at 1.485Gb/s
Š 440m at 270Mb/s
• Integrated Reclocker with low phase noise, integrated
VCO
• Serial digital reclocked, or non-reclocked output
• Integrated audio de-embedder for 8 channels of 48kHz
audio
• Integrated audio clock generator
• Ancillary data extraction
• Parallel data bus selectable as either 20-bit or 10-bit
• Comprehensive error detection and correction
features
• Output H, V, F or CEA 861 Timing Signals
• 1.2V digital core power supply, 1.2V and 3.3V analog
power supplies, and selectable 1.8V or 3.3V I/O power
supply
• GSPI Host Interface
• Wide temperature range of -40ºC to +85ºC
• Low power operation (typically 480mW)
• Small 11mm x 11mm 100-ball BGA package
• Pb-free and RoHS compliant
Applications
Application: 1080p30 or 720p60 Monitor
HD-SDI
AES - OUT
GS1671A
AUDIO 1/2
AUDIO 3/4
AUDIO 5/6
AUDIO 7/8
Audio Clocks
Audio
Selector
10-bit
HV F/PCLK
Video
Processor
C TR L/TIMECODE
DAC
Speakers
DAC
Display
Application: Multi-format Downconverter
10-bit SD Bypass
Memory
SD/HD-SDI
GS1671A
10-bit
HV F/PCLK
Video
Downconverter &
Aspect Ratio
Conversion
Analog
Sync
Sync
Seperator
AE S 1/2
AE S 3/4
AE S 5/6
AE S 7/8
Audio
Processing
& Delay
GS4901
Audio Clocks
HV F/PCLK
AE S 1/2
AE S 3/4
AE S 5/6
AE S 7/8
10-bit
HD/SD
Serializer
(GS1672)
HD/SD-SDI
Application: Multi-input Video Monitoring System
HD-SDI
Input 1
HD-SDI
Input 2
GS1671A
10-bit
HV F/PCLK
GS1671A
10-bit
HV F/PCLK
Video
Memory
Video
Formatter
H V/DE/PCLK
DVI/
VGA DAC
Video
Output
HD-SDI
Input n
GS1671A
10-bit
HV F/PCLK
Analog
Sync
Sync
Seperator
AES BUS
GS4911
Audio
Select
HV F/PCLK
Audio Clocks
On Screen
Display
Generator
Audio
Processor
AE S OUT 1/2
AE S OUT 3/4
AE S OUT 5/6
AE S OUT 7/8
GS1671A HD/SD SDI Receiver
Data Sheet
54389 - 1
September 2012
www.semtech.com
1 of 136






GS1671A Datasheet, Funktion
List of Figures
Figure 3-1: Digital Input Pin with Schmitt Trigger............................................................................... 23
Figure 3-2: Bidirectional Digital Input/Output Pin.............................................................................. 23
Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive strength ........ 24
Figure 3-4: XTAL1/XTAL2/XTAL-OUT ................................................................................................... 24
Figure 3-5: VBG .............................................................................................................................................. 24
Figure 3-6: LB_CONT .................................................................................................................................... 25
Figure 3-7: Loop Filter .................................................................................................................................. 25
Figure 3-8: SDO/SDO .................................................................................................................................... 25
Figure 3-9: Equalizer Input Equivalent Circuit .................................................................................... 25
Figure 4-1: GS1671A Integrated EQ Block Diagram .......................................................................... 28
Figure 4-2: 27MHz Clock Sources ............................................................................................................ 30
Figure 4-3: PCLK to Data and Control Signal Output Timing - SDR Mode 1 .............................. 34
Figure 4-4: PCLK to Data and Control Signal Output Timing - SDR Mode 2 .............................. 35
Figure 4-5: Switch Line Locking on a Non-Standard Switch Line ................................................. 39
Figure 4-6: H:V:F Output Timing - HDTV 20-bit Mode ..................................................................... 43
Figure 4-7: H:V:F Output Timing - HDTV 10-bit Mode ..................................................................... 43
Figure 4-8: H:V:F Output Timing - HD 20-bit Output Mode ............................................................ 43
Figure 4-9: H:V:F Output Timing - HD 10-bit Output Mode ............................................................ 44
Figure 4-10: H:V:F Output Timing - SD 20-bit Output Mode .......................................................... 44
Figure 4-11: H:V:F Output Timing - SD 10-bit Output Mode .......................................................... 44
Figure 4-12: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4) ................................... 46
Figure 4-13: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5) ................................. 46
Figure 4-14: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7) .................... 47
Figure 4-15: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19) ............................................. 47
Figure 4-16: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20) ........................................... 48
Figure 4-17: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22) ........................... 49
Figure 4-18: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32) .............................. 49
Figure 4-19: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33) .......................................... 50
Figure 4-20: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34) .............................. 50
Figure 4-21: 2K Feature Enhancement ................................................................................................... 53
Figure 4-22: Y/1ANC and C/2ANC Signal Timing .............................................................................. 60
Figure 4-23: Ancillary Data Extraction - Step A .................................................................................. 66
Figure 4-24: Ancillary Data Extraction - Step B ................................................................................... 67
Figure 4-25: Ancillary Data Extraction - Step C .................................................................................. 67
Figure 4-26: Ancillary Data Extraction - Step D .................................................................................. 68
Figure 4-27: ACLK to Data Signal Output Timing ............................................................................... 70
Figure 4-28: I2S Audio Output Format .................................................................................................... 71
Figure 4-29: AES/EBU Audio Output Format ....................................................................................... 71
Figure 4-30: Serial Audio, Left Justified, MSB First ............................................................................. 72
Figure 4-31: Serial Audio, Left Justified, LSB First .............................................................................. 72
Figure 4-32: Serial Audio, Right Justified, MSB First .......................................................................... 72
Figure 4-33: Serial Audio, Right Justified, LSB First ........................................................................... 72
Figure 4-34: AES/EBU Audio Output to Bit Clock Timing ................................................................ 72
Figure 4-35: ECC 24-bit Array and Examples ...................................................................................... 75
Figure 4-36: Sample Distribution Over Five Video Frames (525-line Systems) ........................ 76
Figure 4-37: Audio Buffer After Initial 26 Sample Write .................................................................. 77
Figure 4-38: Audio Buffer Pointer Boundary Checking .................................................................... 77
Figure 4-39: GSPI Application Interface Connection ........................................................................ 83
Figure 4-40: Command Word Format ..................................................................................................... 83
Figure 4-41: Data Word Format ................................................................................................................ 84
Figure 4-42: Write Mode .............................................................................................................................. 85
GS1671A HD/SD SDI Receiver
Data Sheet
54389 - 1
September 2012
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6 Page









GS1671A pdf, datenblatt
Table 1-1: Pin Descriptions (Continued)
Pin
Number
F7
Name
CS_TMS
Timing
Type
Input
F8 SCLK_TCK
Input
F9, F10, H9,
H10, J8, J9,
J10, K8, K9,
K10
DOUT8, 9, 6, 7, 1,
4, 5, 0, 2, 3
Output
G3 RC_BYP
Input
Description
COMMUNICATION SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Chip select / test mode start.
In JTAG mode (JTAG/HOST = HIGH), this pin is Test Mode Start, used
to control the operation of the JTAG test.
In host interface mode (JTAG/HOST = LOW), this pin operates as the
host interface chip select and is active LOW.
COMMUNICATION SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Serial data clock signal.
In JTAG mode (JTAG/HOST = HIGH), this pin is the JTAG clock.
In host interface mode (JTAG/HOST = LOW), this pin is the host
interface serial bit clock.
All JTAG/host interface addresses and data are shifted into/out of
the device synchronously with this clock.
PARALLEL DATA BUS
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
20-bit mode
20bit/10bit = HIGH
SMPTE mode (SMPTE_BYPASS = HIGH
and DVB_ASI = LOW):
Chroma data output for SD and HD
data rates
DVB-ASI mode (SMPTE_BYPASS = LOW
and DVB_ASI = HIGH):
Not defined
Data-Through mode (SMPTE_BYPASS =
LOW and DVB_ASI = LOW):
Data output
10-bit mode
20bit/10bit = LOW
Forced LOW
CONTROL SIGNAL INPUT
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
When this pin is LOW, the serial digital output is the buffered
version of the input serial data. When this pin is HIGH, the serial
digital output is the reclocked version of the input serial data.
GS1671A HD/SD SDI Receiver
Data Sheet
54389 - 1
September 2012
12 of 136

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