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CH7034B Schematic ( PDF Datasheet ) - Chrontel

Teilenummer CH7034B
Beschreibung HDTV/VGA/LVDS Encoder
Hersteller Chrontel
Logo Chrontel Logo 




Gesamt 9 Seiten
CH7034B Datasheet, Funktion
Chrontel
CH7034B
Brief Datasheet
CH7034B HDTV/VGA/LVDS Encoder
FEATURES
GENERAL DESCRIPTIONS
Supports multiple output display formats – including Chrontel CH7034B is specifically designed for a portable
Component YPrPb(HDTV), LVDS and analog RGB system that requires connections to LCD display, High
(VGA)
Definition Television (HDTV) or RGB (VGA) monitor.
Three 10-bit high speed DACs
With its advanced video encoder, flexible scaling engine
HDTV output support up to 1080p
and easy-to-configure video interface, the CH7034B
Analog RGB (VGA) support up to 1920x1080 satisfies manufactures’ product display requirements and
resolution
reduces their costs of development and time-to-market.
Single channel LVDS 18-bit transmitter supports
input resolution up to 1366x768
The CH7034B provides analog RGB and YPrPb outputs
Support scaled and bypassed video streams output that allow a system to display high definition media
from VGA/HDTV and LVDS interfaces content to HDTV/RGB monitors. The device is
simultaneously
compliant with EIA770-3 and SMPTE 274M/293M
Supports panel protection, power sequencing and /296M standards and supports HDTV resolution up to
backlight on/off. PWM is available for controlling 1080p. The 3 high-performance, 10-bit DACs can be
LCD brightness
used for either HDTV display or VGA output. The
TV/Monitor connection detect capability. DACs can CH7034B has the ability to generate composite syncs if
be switched off through programming internal required by the RGB monitor.
registers
On-chip SDRAM frame buffer to support frame rate To support portable computer with LCD display, the
conversion.
CH7034B has incorporated an one-channel, 18-bit output
Programmable adaptive de-flickering filter
LVDS transmitter. On-chip dithering function is
Supports 8/12/16/18/24-bit parallel interface inputs available to convert 24-bit color to 18-bit color LCD
for either RGB format or YCbCr format (ITU-R 656 panels. Two popular LVDS standards, the OpenLDI and
or ITU-R 601). 80/86 MPU interface and DE only the VESA SPWG are supported by the CH7034B LVDS
mode are also supported.
driver. The preferred standard and its display timing can
Wide range of input resolutions support for up to be configured through devices’ registers when system is
1366x768 (i.e. 640x480 720x480, 720x576, 800x600, powered on.
1024x600, 1024x768, 1280x800, and etc.)
Image display rotation support at 90/180/270 degree The CH7034B is equipped with panel protection
or flipped in horizontal/vertical position
mechanism to switch off the LCD instantly if input data
Pixel-level color enhancement for brightness, is missing or unstable. The panel on/off sequences and
contrast, hue and saturation adjustment for HDTV backlight control can be configured through
Horizontal/vertical position adjusted through serial programming internal registers. In addition, a built-in
port programming
PWM function can be used to achieve digital dimming
Pixel clock input frequency support for up to 165 for LCD panel.
MHz
Flexible crystal or oscillator clock input frequency The CH7034B converts a wide range of input formats to
(2.3MHz – 64MHz)
HDTV/VGA outputs and LVDS display. RGB data
IO Supply Voltages from 1.2V to 3.3V and SPC/SPD format such as 16-bit 5:6:5, 18-bit 6:6:6 or 24-bit 8:8:8
Supply Voltages from 1.8V to 3.3V.
enters through the device’s 24-bit bus. In YCrCb format,
Programmable power management
either 24-bit 4:4:4 data or 16-bit 4:2:2 is supported by the
Device fully programmable through serial port or can CH7034B’s color space converter. The device’s video
automatically load firmware from Chrontel Boot capture block also has an option to support 80/86 MPU
ROM (CH9904)
Offered in a 88-pin QFN package
interface. The input video signal can be either interlaced
or non-interlaced data formats.
201-1000-028 Rev. 1.22 11/19/2013
With its embedded high speed SDRAM, the CH7034B
can help manufactures design their products to achieve
simultaneous LVDS and HDTV/VGA display. Thanks to
the sophisticated scaler, the input LCD data with low
resolution or reduced-frame rate can be covert to high
1






CH7034B Datasheet, Funktion
CHRONTEL
69
In/Out
SPDM
72 Out SPCM
74 Out DAC2
76 Out DAC1
78 Out DAC0
80 In
ISET
81
Output
IRQ
82 In
GCLK
84 In
DE/CSB
85
In/Out
V
86
In/Out
H/WEB
24,43,44, N/A
51,65, 66
9,60 Power
59,11
Power
10,42
Power
45 Power
23,46
Power
22,47
Power
30,41
Power
33,38
Power
6
NC
VDDMS
GNDMS
DVDD
DGND
AVDD
AGND
VDDH
VSSH
CH7034B
XO. However, an external 3.3V CMOS compatible clock can drive the
XI/FIN input.
Routed Serial Port Data to CH9904 BOOT ROM
This pin functions as the bi-directional data pin of the serial port to
CH9904 BOOT ROM. This pin will require a pull-up 6.8 Kresistor
to the desired voltage level. A pull-low resistor 10K to ground if
unused.
Routed Serial Port Clock Output to CH9904 BOOT ROM
This pin functions as the clock bus of the serial port to CH9904 BOOT
ROM. This pin will require a pull-up 6.8 Kresistor to the desired
voltage level. A pull-low resistor 10 Kto ground if unused.
YpbPr or Analog RGB output
Full swing is up to 1.3V
YpbPr or Analog RGB output
Full swing is up to 1.3V
YpbPr or Analog RGB output
Full swing is up to 1.3V
Current Set Resistor Input
This pin sets the DAC current. A 1.2 K, 1% tolerance resistor should
be connected between this pin and AGND_DAC using short and wide
traces.
Programmed Interrupt output.
External Clock Inputs
The input is the clock signal input to the device for use with the H, V,
DE and D[23:0] data.
Data Input Indicator
When the pin is high, the input data is active.
When the pin is low, the input data is blanking.
It is also a CSB signal input of CPU interface
The amplitude will be 0 to VDDIO.
Vertical Sync Input/Output
When the SYO control bit is low, this pin accepts a vertical sync input
for use with the input data. The amplitude will be 0 to VDDIO.
When the SYO control bit is high, the device will output a vertical
sync pulse. The output is driven from the VDDIO supply.
Horizontal Sync Input / Output
When the SYO control bit is low, this pin accepts a horizontal sync
input for use with the input data. The amplitude will be 0 to VDDIO.
When the SYO control bit is high, the device will output a horizontal
sync pulse. The output is driven from the VDDIO supply.
It is also the WEB signal of CPU interface.
Not Connect
These pins should be left open.
SDRAM Power Supply (3.3V)
SDRAM Ground
Digital Power Supply (1.8V)
Digital Ground
Analog Power Supply (2.5V-3.3V)
Analog Ground
LVDS Power Supply (3.3V)
LVDS Ground
201-1000-028 Rev. 1.22 11/19/2013

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