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Teilenummer | EM484M1644VTC |
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Beschreibung | 64Mb (1M x 4Bank x 16) Synchronous DRAM | |
Hersteller | Eorex | |
Logo | ||
Gesamt 17 Seiten eorex
EM484M1644VTC
64Mb (1M×4Bank×16) Synchronous DRAM
Features
• Fully Synchronous to Positive Clock Edge
• Single 3.3V ±0.3V Power Supply
• LVTTL Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are Sampled at the Rising Edge of
the System Clock
• Auto Refresh and Self Refresh
• 4,096 Refresh Cycles / 64ms (15.625us)
Description
The EM484M1644VTC is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
1Meg words x 4 banks by 16 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 64Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVTTL.
Available packages:TSOPII 54P 400mil.
Ordering Information
Part No
EM484M1644VTC-7F
EM484M1644VTC-6F
EM484M1644VTC-7FE
EM484M1644VTC-6FE
Organization
4M X 16
4M X 16
4M X 16
4M X 16
Max. Freq
143MHz @CL3
166MHz @CL3
143MHz @CL3
166MHz @CL3
Package
54pin TSOP(ll)
54pin TSOP(ll)
54pin TSOP(ll)
54pin TSOP(ll)
Grade
Commercial
Commercial
Extended
Extended
Pb
Free
Free
Free
Free
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eorex
Block Diagram
EM484M1644VTC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA0
BA1
Auto/Self
Refresh Counter
DQM
Memory
Array
S/A & I/O Gating
Col. Decoder
Write DQM
Control
Data In
Data Out
Col. Add. Buffer
Mode Register Set
Col. Add. Counter
Burst Counter
Read DQM
Control
Timing Register
CLK CKE /CS /RAS /CAS /WE DQM
DOi
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6 Page eorex
EM484M1644VTC
2. DQM Truth Table
Command
Symbol
CKE
n-1 n
Data Write/Output Enable
Data Mask/Output Disable
ENB
MASK
HX
HX
Upper Byte Write Enable/Output Enable
BSTH
HX
Read
READ
HX
Read with Auto Pre-charge
READA
HX
Write
WRIT
HX
Write with Auto Pre-charge
WRITA
HX
Bank Activate
ACT
HX
Pre-charge Select Bank
PRE
HX
Pre-charge All Banks
PALL
HX
Mode Register Set
MRS
HX
H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
/CS
H
L
L
L
L
L
L
L
L
L
L
3. CKE Truth Table
Item
Activating
Any
Clock
Suspend
Idle
Command
Clock Suspend Mode Entry
Clock Suspend Mode
Clock Suspend Mode Exit
CBR Refresh Command
CKE
Symbol
/CS /RAS
n-1 n
HL X X
LLX X
LHX X
REF H H L L
Idle Self Refresh Entry
Self Refresh Self Refresh Exit
SELF
HL L
LH L
LHH
L
H
X
Idle Power Down Entry
HL X X
Power Down Power Down Exit
LHX X
Remark H = High level, L = Low level, X = High or Low level (Don't care)
/CAS /WE
XX
XX
XX
LH
LH
HH
XX
XX
XX
Addr.
X
X
X
X
X
X
X
X
X
May. 2013
12/17
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12 Page | ||
Seiten | Gesamt 17 Seiten | |
PDF Download | [ EM484M1644VTC Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
EM484M1644VTA | 64Mb SDRAM | Eorex |
EM484M1644VTC | 64Mb (1M x 4Bank x 16) Synchronous DRAM | Eorex |
EM484M1644VTD | 64Mb Synchronous DRAM | Eorex |
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