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EM44DM0888LBA Schematic ( PDF Datasheet ) - Eorex

Teilenummer EM44DM0888LBA
Beschreibung Double DATA RATE SDRAM
Hersteller Eorex
Logo Eorex Logo 




Gesamt 29 Seiten
EM44DM0888LBA Datasheet, Funktion
Revision History
Revision 0.1 (Feb. 2011)
-First release.
Revision 0.2 (Jan.2013)
-Add speed 1066.
EM44DM0888LBA
Feb. 2012
1/29
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EM44DM0888LBA Datasheet, Funktion
EM44DM0888LBA
Pin Description (Continued)
B3,A2,B7,A8
B3
C8,C2,D7,D3,
D1,D9,B1,B9
RDQS,/RDQS
, DQS,/DQS
DM
DQ0~7
(Data Strobe)
Output with read data, input with write data. Edge-aligned with read
data, centered in write data. An RDQS option using DM pin can be
enabled via the EMRS(1) to simplify read timing.
The data strobes DQS and RDQS may be used in single ended mode
or paired with optional complimentary signals /DQS and /RDQS to
provide differential pair signaling to the system during both reads and
writes. An EMRS(1) control bit enables or disables all complementary
data strobe signals.
(Data Mask)
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH coincident with that input data during a Write
access. DM is sampled on both edges of DQS. Although DM pins are
input only, the DM loading matches the DQ and DQS loading. DM is
enabled by EMRS command.
(Data Input/Output)
Data inputs and outputs are on the same pin.
A1,L1,E9,H9/
A3,E3,J1,K9
VDD/VSS
(Power Supply/Ground)
VDD and VSS are power supply for internal circuits.
A9,C1,C3,C7,
C9/A7,B2,B8,
D2,D8
E1/E7
E2
L3,L7
(DQ Power Supply/DQ Ground)
VDDQ/VSSQ VDDQ and VSSQ are power supply for the output buffers.
VDDL/VSSDL
VREF
NC
(DLL Power Supply/DLL Ground)
VDDL and VSSDL are power supply for DLL circuits
(Reference Voltage)
SSTL_1.8 reference voltage
(No Connection)
No internal electrical connection is present.
Feb. 2012
6/29
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6 Page









EM44DM0888LBA pdf, datenblatt
EM44DM0888LBA
AC Operating Test Characteristics
(VDD=1.8V±0.1V)
Symbol
Parameter
tAC
tDQSCK
tCL,tCH
tCK
tDS
tDH
tDIPW
tHZ
DQ output access from CLK,/CLK
DQS output access from CLK,/CLK
CL low/high level width
Clock Cycle Time
DQ and DM setup time
DQ and DM hold time
DQ and DM input pulse width for each
input
Data out high impedance time from
CLK,/CLK
tLZ (DQ) DQ low impedance time from CLK,/CLK
tLZ (DQS)
tDQSQ
tQHS
tDQSS
tDQSL,tDQSH
tDSL,tDSH
tMRD
tWPRES
tWPRE
tWPST
tIS
tIH
tRPRE
DQS,/DQS low impedance time from
CLK,/CLK
DQS-DQ skew for associated DQ signal
Data hold skew factor
Write command to first latching DQS
transition
DQS Low/High input pulse width
DQS input valid window
Mode Register Set command cycle time
Write Preamble setup time
Write Preamble
Write Postamble
Address/control input setup time (fast
slew rate)
Address/control input hold time
(fast slew rate)
Read Preamble
-187 (DDR2-1066)
Min. Max.
-350
350
-350
0.48
1.875
0
75
350
0.52
8
-
-
0.35 -
-
2*tAC
(min)
tAC
(min)
-
-
tAC
(max)
tAC
(max)
tAC
(max)
175
250
-0.25
0.25
0.35 -
0.20 -
2-
0-
0.35 -
0.4 0.6
125 -
200 -
0.9 1.1
-25 (DDR2-800)
Min. Max.
-400
400
-350
0.48
2.5
50
125
350
0.52
8
-
-
0.35 -
-
2*tAC
(min)
tAC
(min)
-
-
tAC
(max)
tAC
(max)
tAC
(max)
200
300
-0.25
0.25
0.35 -
0.20 -
2-
0-
0.35 -
0.4 0.6
175 -
Units
ps
ps
tCK
ns
ps
ps
tCK
ns
ns
ns
ps
ps
tCK
tCK
tCK
tCK
ns
tCK
tCK
ps
250 - ps
0.9 1.1 tCK
Feb. 2012
12/29
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12 Page





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