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P3204M2S5X2 Schematic ( PDF Datasheet ) - Apollo Memory System

Teilenummer P3204M2S5X2
Beschreibung Embedded MCP
Hersteller Apollo Memory System
Logo Apollo Memory System Logo 




Gesamt 30 Seiten
P3204M2S5X2 Datasheet, Funktion
eMCP Specification
Embedded MCP specification
P3204M2S5X2
Datasheet Preliminary Ver 1.0
Apollo Memory System Company
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© 2014 Apollo memory system company
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CONFIDENTIAL






P3204M2S5X2 Datasheet, Funktion
eMCP Specification
Name
CID
RCA
DSR
CSD
OCR
EXT_CSD
Width
(bytes)
16
2
2
16
4
512
Table 4 eMMCRegisters
Description
Device Identification number, an individual number for identification.
Relative Device Address, is the Device system address, dynamically
assigned by the host during initialization.
Driver Stage Register, to configure the Device’s output drivers.
Device Specific Data, information about the Device operation conditions.
Operation Conditions Register. Used by a special broadcast command to
identify the voltage type of the Device.
Extended Device Specific Data. Contains information about the Device
capabilities and selected modes. Introduced in standard v4.0
Implementation
Mandatory
Mandatory
Optional
Mandatory
Mandatory
Mandatory
The host may reset the device by:
Switching the power supply off and back on. The device shall have its own power-on detection
circuitry which puts the device into a defined state after the power-on Device.
A reset signal
By sending a special command
____________________________________________________________________________________________________________________
© 2014 Apollo memory system company
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6 Page









P3204M2S5X2 pdf, datenblatt
eMCP Specification
3.1.2 e•MMC™ Power Cycling
The master can execute any sequence of VCC and VCCQ power-up/power-down. However, the master
must not issue any commands until VCC and VCCQ are stable within each operating voltage range.
After the slave enters sleep mode, the master can power-down VCC to reduce power consumption. It
is necessary for the slave to be ramped up to VCC before the host issues CMD5 (SLEEP_AWAKE) to
wake the slave unit. For more information about power cycling see Section 10.1.3 of the JEDEC
Standard Specification No.JESD84-B50.
Figure 7 The e•MMCPower Cycle
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© 2014 Apollo memory system company
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