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PDF ADP3209D Data sheet ( Hoja de datos )
| Número de pieza | ADP3209D | |
| Descripción | Synchronous Buck Controller | |
| Fabricantes | ON Semiconductor | |
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ADP3209D
5-Bit, Programmable,
Single-Phase, Synchronous
Buck Controller
The ADP3209D is a highly efficient, single−phase, synchronous
buck switching regulator controller. With its integrated drivers, the
ADP3209D is optimized for converting the notebook battery voltage
to render the supply voltage required by high performance Intel
chipsets. An internal 5−bit DAC is used to read a VID code directly
from the chipset and to set the GMCH core voltage to a value within
the range of 0.4 V to 1.25 V.
The ADP3209D uses a multi−mode architecture. It provides
programmable switching frequency that can be optimized for
efficiency depending on the output current requirement. In addition,
the ADP3209D includes a programmable load line slope function to
adjust the output voltage as a function of the load current so that the
core voltage is always optimally positioned for a load transient. The
ADP3209D also provides accurate and reliable current overload
protection and a delayed power−good output. The IC supports
On−The−Fly (OTF) output voltage changes requested by the chipset.
The ADP3209D is specified over the extended commercial
temperature range of 0°C to 100°C and is available in a 32−lead
LFCSP.
Features
• Single−Chip Solution
• Fully Compatible with the Intel® GMCH Chipset Voltage Regulator
Specifications
• Integrated MOSFET Drivers
• Input Voltage Range of 3.3 V to 22 V
• ±8 mV Worst−Case Differentially Sensed Core Voltage Error
Overtemperature
• Automatic Power−Saving Modes Maximize Efficiency During Light
Load Operation
• Soft Transient Control Reduces Inrush Current and Audio Noise
• Independent Current Limit and Load Line Setting Inputs for
Additional Design Flexibility
• Built−In Power−Good Masking Supports Voltage Identification
(VID) OTF Transients
• 5−Bit, Digitally Programmable DAC with 0.4 V to 1.25 V Output
• Short−Circuit Protection with Latchoff Delay
• Output Current Monitor
• 32−Lead LFCSP
• This is a Pb−Free Device
Applications
• Notebook Power Supplies for Next−Generation Intel Chipsets
http://onsemi.com
LFCSP32
CASE 932AE
MARKING DIAGRAM
ADP3209D
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YYWW = Date Code
G = Pb−Free Package
PIN ASSIGNMENT
FBRTN
FB
COMP
CREF
NC
IMON
IREF
RPM
32 25
1 24
ADP3209D
(top view)
8 17
9 16
VCC
BST
DRVH
SW
PVCC
DRVL
PGND
GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 26 of this data sheet.
© Semiconductor Components Industries, LLC, 2010
March, 2010 − Rev. 0
1
Publication Order Number:
ADP3209D/D
1 page  
ADP3209D
ELECTRICAL CHARACTERISTICS VCC = 5.0V, FBRTN = GND, VARFREQ = Low, VVID = 1.25 V, TA = −10°C to 100°C, unless
otherwise noted (Note 1). Current entering a pin (sunk by the device) has a positive sign. RREF = 80 kW.
Parameter
Symbol
Conditions
Min Typ Max Unit
VOLTAGE MONITORING AND PROTECTION − Power Good
PWRGD Latchoff Delay TLOFFPWRGD Measured from Out−off−Good−Window event to 8.0 ms
Latchoff (switching stops)
PWRGD Propagation
TPDPWRGD
Measured from Out−off−Good−Window event to
200
ns
Delay (Note 3)
PWRGD neg edge
Crowbar Latchoff Delay
(Note 2)
TLOFFCB
Measured from Crowbar event to Latchoff
(switching stops)
200 ns
PWRGD Masking Time
CSREF Soft−Stop
Resistance
Triggered by any VID change or OCP event
EN = L or Latchoff condition
100 ms
70 W
CURRENT CONTROL − Current Sense Amplifier (CSAMP)
CSSUM, CSREF
Common−Mode Range
(Note 2)
Voltage range of interest
0 2.0 V
CSSUM, CSREF Offset
Voltage
VOSCSA
CSSUM Bias Current
IBCSSUM
CSREF Bias Current
IBCSREF
CSCOMP Voltage Range (Note 2)
CSREF − CSSUM, TA = 25°C
TA = −10°C to 85°C
Voltage range of interest
−0.5
−1.6
−50
−2.0
0.05
+0.5 mV
+1.6
+50 nA
+2.0 mA
2.0 V
CSCOMP Current
CSCOMP Slew Rate
ICSCOMPsource
ICSCOMPsink
CSCOMP = 2.0 V
CSSUM forced 200 mV below CSREF
CSSUM forced 200 mV above CSREF
CCSCOMP = 10 pF
CSSUM forced 200 mV below CSREF
CSSUM forced 200 mV above CSREF
−470
1.0
10
−10
mA
mA
V/ms
Gain Bandwidth
(Note 2)
GBWCSA
Non−inverting unit gain configuration, RFB = 1 kW
20
MHz
CURRENT MONITORING AND PROTECTION
Current Reference
IREF Voltage
Current Limiter (OCP)
Current Limit Threshold
Current Limit Latchoff
Delay
VREF
VLIMTH
RREF = 80 kW to set IREF = 20 mA
Measured from CSCOMP to CSREF, RLIM = 4.5 kW
Measured from OCP event to PWRGD
de−assertion
1.55
−70
1.6 1.65
−90 −110
2.0
V
mV
ms
Current Monitor
Current Gain Accuracy
IMON/ILIM
Measured from ILIMP to IMON
ILIM = −20 mA
ILIM = −10 mA
ILIM = −5 mA
IMON Clamp Voltage
VMAXMON
Relative to FBRTN
PULSE WIDTH MODULATOR − Clock Oscillator
9.4 10 10.7
9.2 10 11.0
9.0 10 11.3
1.0 1.15 V
RT Voltage
PWM Clock Frequency
Range (Note 2)
VRT VARFREQ = Low, RT = 120 kW,
VVID = 1.2500 V
VARFREQ = High
See also VRT(VVID) formula
fCLK Operation of interest
1.07 1.125 1.17
1.0 5.0
5.0
0.95 1.05
0.3 3.0
V
MHz
PWM Clock Frequency
fCLK TA = +25°C, VVID = 1.2000 V
RT = 73 kW (Note 2)
RT = 125 kW
RT = 180 kW (Note 2)
970 1270 157
705 830
0
500
600
955
750
kHz
1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
3. Timing is referenced to the 90% and 10% points, unless otherwise noted.
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5
5 Page 
ADP3209D
5.0 V
IR = A R y IRAMP
CLOCK
OSCILLATOR
CR
FLIP−FLOP
SQ
RD
BST1
GATE DRIVER
BST
DRVH
IN SW
DRVH1
SW1
DRVL
DRVL1
VCC
RI L
VCC
AD
0.2 V
RAMP
COMP
VDC
+ć
+ VCS
+
–
+
FB
FBRTN LLINE
CSCOMP
RA CA
CFB
CB
RB
CSREF
CSSUM
RCS
CCS
RPH
LOAD
Figure 14. PWM Mode Operation
Setting Switch Frequency
Master Clock Frequency in PWM Mode
When the ADP3209D runs in PWM, the clock frequency
is set by an external resistor connected from the RT pin to
GND. The frequency varies with the VID voltage: the lower
the VID voltage, the lower the clock frequency. The
variation of clock frequency with VID voltage maintains
constant VCGFX ripple and improves power conversion
efficiency at lower VID voltages.
Switching Frequency in RPM Mode
When the ADP3209D operates in RPM mode, its switching
frequency is controlled by the ripple voltage on the COMP
pin. Each time the COMP pin voltage exceeds the RPM pin
voltage threshold level determined by the VID voltage and
the external resistor connected between RPM and GND, an
internal ramp signal is started and DRVH is driven high. The
slew rate of the internal ramp is programmed by the current
entering the RAMP pin. One−third of the RAMP current
charges an internal ramp capacitor (5 pF typical) and creates
a ramp. When the internal ramp signal intercepts the COMP
voltage, the DRVH pin is reset low.
In continuous current mode, the switching frequency of
RPM operation is almost constant. While in discontinuous
current conduction mode, the switching frequency is
reduced as a function of the load current.
Differential Sensing of Output Voltage
The ADP3209D combines differential sensing with a high
accuracy VID DAC, referenced by a precision band gap
source and a low offset error amplifier, to meet the rigorous
accuracy requirement of the Intel IMVP−6+ specification.
In steady−state mode, the combination of the VID DAC and
error amplifier maintain the output voltage for a worst−case
scenario within ±8 mV of the full operating output voltage
and temperature range.
The VCCGFX output voltage is sensed between the FB and
FBRTN pins. FB should be connected through a resistor to
the positive regulation point; the VCC remote sensing pin of
the GMCH. FBRTN should be connected directly to the
negative remote sensing point; the VSS sensing point of the
GMCH. The internal VID DAC and precision voltage
reference are referenced to FBRTN and have a typical current
of 200 mA for guaranteed accurate remote sensing.
Output Current Sensing
The ADP3209D includes a dedicated current sense
amplifier (CSA) to monitor the total output current of the
converter for proper voltage positioning vs. load current and
for overcurrent detection. Sensing the current delivered to
the load is an inherently more accurate method than
detecting peak current or sampling the current across a sense
element, such as the low−side MOSFET. The current sense
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11
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| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet ADP3209D.PDF ] | |
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