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DP8405 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer DP8405
Beschreibung Error Detection and Correction Circuits
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 18 Seiten
DP8405 Datasheet, Funktion
PRELIMINARY
August 1989
DP8402A DP8403 DP8404 DP8405 32-Bit Parallel
Error Detection and Correction Circuits (EDAC’s)
General Description
The DP8402A DP8403 DP8404 and DP8405 devices are
32-bit parallel error detection and correction circuits
(EDACs) in 52-pin DP8402A and DP8403 or 48-pin DP8404
and DP8405 600-mil packages The EDACs use a modified
Hamming code to generate a 7-bit check word from a 32-bit
data word This check word is stored along with the data
word during the memory write cycle During the memory
read cycle the 39-bit words from memory are processed by
the EDACs to determine if errors have occurred in memory
Single-bit errors in the 32-bit data word are flagged and cor-
rected
Single-bit errors in the 7-bit check word are flagged and the
CPU sends the EDAC through the correction cycle even
though the 32-bit data word is not in error The correction
cycle will simply pass along the original 32-bit data word in
this case and produce error syndrome bits to pinpoint the
error-generating location
Double bit errors are flagged but not corrected These er-
rors may occur in any two bits of the 39-bit word from mem-
ory (two errors in the 32-bit data word two errors in the 7-bit
check word or one error in each word) The gross-error
condition of all lows or all highs from memory will be detect-
ed Otherwise errors in three or more bits of the 39-bit word
are beyond the capabilities of these devices to detect
Read-modify-write (byte-control) operations can be per-
formed with the DP8402A and DP8403 EDACs by using out-
put latch enable LEDBO and the individual OEB0 thru
OEB3 byte control pins
Diagnostics are performed on the EDACs by controls and
internal paths that allow the user to read the contents of the
DB and CB input latches These will determine if the failure
occurred in memory or in the EDAC
Features
Y Detects and corrects single-bit errors
Y Detects and flags double-bit errors
Y Built-in diagnostic capability
Y Fast write and read cycle processing times
Y Byte-write capability DP8402A and DP8403
Y Fully pin and function compatible with TI’s
SN74ALS632A thru SN74ALS635 series
System Environment
TL F 8535 – 1
TRI-STATE is a registered trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation TL F 8535
RRD-B30M105 Printed in U S A






DP8405 Datasheet, Funktion
TABLE VI Read-Modify-Write Function
MEMORY
EDAC FUNCTION
CYCLE
Read
Read Flag
Read
Latch input data
check bits
Read
Latch corrected
data word into
output latch
Modify
write
Modify appropriate
byte or bytes
generate new
check word
CONTROL
S1 S0
HL
HH
HH
LL
BYTEn OEBn
Input
Input
data
latched
Output
data
word
latched
Input
modified
BYTE0
Ouput
unchanged
BYTE0
H
H
H
H
L
DB OUTPUT
LATCH
LEDBO
CB
CHECK I O
CONTROL
X
Input
H
Input
L
check word
H
latched
Hi-Z H
H Output
Syndrome
L
bits
H
Output
check word
L
ERROR FLAG
ERR MERR
Enabled
Enabled
Enabled
HH
OEB0 controls DB0–DB7 (BYTE0) OEB1 controls DB8–DB15 (BYTE1) OEB2 controls DB16–DB23 (BYTE2) OEB3 controls DB24–DB31 (BYTE3)
Read-Modify-Write (Byte Control)
Operations
The DP8402A and DP8403 devices are capable of byte-
write operations The 39-bit word from memory must first be
latched into the DB and CB input latches This is easily ac-
complished by switching from the read and flag mode (S1 e
H SO e L) to the latch input mode (S1 e H S0 e H) The
EDAC will then make any corrections if necessary to the
data word and place it at the input of the output data latch
This data word must then be latched into the output data
latch by taking LEDBO from a low to a high
Byte control can now be employed on the data word
through the OEB0 through OEB3 controls OEB0 controls
DB0 – DB7 (byte 0) OEB1 controls DB8–DB15 (byte 1)
OEB2 controls DB16–DB23 (byte 2) and OEB3 controls
DB24 – DB31 (byte 3) Placing a high on the byte control will
disable the output and the user can modify the byte If a low
is placed on the byte control then the original byte is al-
lowed to pass onto the data bus unchanged If the original
data word is altered through byte control a new check word
must be generated before it is written back into memory
This is easily accomplished by taking control S1 and S0 low
Table VI lists the read-modify-write functions
Diagnostic Operations
The DP8402A thru DP8405 are capable of diagnostics that
allow the user to determine whether the EDAC or the mem-
ory is failing The diagnostic function tables will help the
user to see the possibilities for diagnostic control
In the diagnostic mode (S1 e L S0 e H) the checkword is
latched into the input latch while the data input remains
transparent This lets the user apply various data words
against a fixed known checkword If the user applies a diag-
nostic data word with an error in any bit location the ERR
flag should be low If a diagnostic data word with two errors
in any bit location is applied the MERR flag should be low
After the checkword is latched into the input latch it can be
verified by taking OECB low This outputs the latched
checkword With the DP8402A and DP8403 the diagnostic
data word can be latched into the output data latch and
verified It should be noted that the DP8404 and DP8405 do
not have this pass-through capability because they do not
contain an output data latch By changing from the diagnos-
tic mode (S1 e L S0 e H) to the correction mode (S1 e H
S0 e H) the user can verify that the EDAC will correct the
diagnostic data word Also the syndrome bits can be pro-
duced to verify that the EDAC pinpoints the error location
Table VII DP8402A and DP8403 and Table VIII DP8404 and
DP8405 list the diagnostic functions
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DP8405 pdf, datenblatt
DP8402A Switching Characteristics
VCC e 4 5V to 5 5V CL e 50 pF TA e Min to Max (unless otherwise noted)
Symbol
From
(Input)
To
(Output)
Test Conditions
tpd
DB and CB
ERR
S1 e H S0 e L RL e 500X
DB
ERR
S1 e L S0 e H RL e 500X
tpd
DB and CB
MERR S1 e H S0 e L RL e 500X
DB MERR S1 e L S0 e H RL e 500X
v vtpd S0 and S1 CB R1 e R2 e 500X
tpd DB CB S1 e L S0 e L R1 e R2 e 500X
vtpd LEDB0 DB S1 e X S0 e H R1 e R2 e 500X
utpd S1 CB S0 e H R1 e R2 e 500X
vten OECB CB S0 e H S1 e X R1 e R2 e 500X
utdis OECB
CB S0 e H S1 e X R1 e R2 e 500X
vten OEB0 thru OEB3 DB S0 e H S1 e X R1 e R2 e 500X
utdis OEB0 thru OEB3
DB S0 e H S1 e X R1 e R2 e 500X
Military
Min Max
10 43
10 43
15 67
15 67
10 60
10 60
7 35
10 60
2 30
2 30
2 30
2 30
Commercial
Min Max
10 40
10 40
15 55
15 55
10 48
10 48
7 30
10 50
2 25
2 25
2 25
2 25
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DP8403 Switching Characteristics
VCC e 4 5V to 5 5V CL e 50 pF TA e Min to Max (unless otherwise noted)
Symbol
From
(Input)
To
(Output)
Test Conditions
Military
Min Typ Max
tpd
DB and CB
ERR
DB ERR
tpd
DB and CB
MERR
v vtpd S0 and S1 CB
tpd DB CB
vtpd LEDB0 DB
utpd S1 CB
utPLH
OECB
CB
vtPHL
OECB
CB
utPLH
OEB0 thru OEB3
DB
vtPHL
OEB0 thru OEB3
DB
All typical values are at VCC e 5V TA e a25 C
S1 e H S0 e L RL e 500X
S1 e L S0 e H RL e 500X
S1 e H S0 e L RL e 500X
S1 e L S0 e H RL e 500X
RL e 680X
S1 e L S0 e L RL e 680X
S1 e X S0 e H RLe 680X
S0 e H RL e 680X
S1 e X S0 e H RL e 680X
S1 e X S0 e H RL e 680X
S1 e X S0 e H RL e 680X
S1 e X S0 e H RL e 680X
26
26
40
40
40
40
26
40
24
24
24
24
Commercial
Min Typ Max
26
26
40
40
40
40
26
40
24
24
24
24
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12

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