PDF DP8402A Data sheet ( Hoja de datos )

Número de pieza	DP8402A
Descripción	Error Detection and Correction Circuits
Fabricantes	National Semiconductor
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PRELIMINARY August 1989 DP8402A DP8403 DP8404 DP8405 32-Bit Parallel Error Detection and Correction Circuits (EDAC’s) General Description The DP8402A DP8403 DP8404 and DP8405 devices are 32-bit parallel error detection and correction circuits (EDACs) in 52-pin DP8402A and DP8403 or 48-pin DP8404 and DP8405 600-mil packages The EDACs use a modified Hamming code to generate a 7-bit check word from a 32-bit data word This check word is stored along with the data word during the memory write cycle During the memory read cycle the 39-bit words from memory are processed by the EDACs to determine if errors have occurred in memory Single-bit errors in the 32-bit data word are flagged and cor- rected Single-bit errors in the 7-bit check word are flagged and the CPU sends the EDAC through the correction cycle even though the 32-bit data word is not in error The correction cycle will simply pass along the original 32-bit data word in this case and produce error syndrome bits to pinpoint the error-generating location Double bit errors are flagged but not corrected These er- rors may occur in any two bits of the 39-bit word from mem- ory (two errors in the 32-bit data word two errors in the 7-bit check word or one error in each word) The gross-error condition of all lows or all highs from memory will be detect- ed Otherwise errors in three or more bits of the 39-bit word are beyond the capabilities of these devices to detect Read-modify-write (byte-control) operations can be per- formed with the DP8402A and DP8403 EDACs by using out- put latch enable LEDBO and the individual OEB0 thru OEB3 byte control pins Diagnostics are performed on the EDACs by controls and internal paths that allow the user to read the contents of the DB and CB input latches These will determine if the failure occurred in memory or in the EDAC Features Y Detects and corrects single-bit errors Y Detects and flags double-bit errors Y Built-in diagnostic capability Y Fast write and read cycle processing times Y Byte-write capability DP8402A and DP8403 Y Fully pin and function compatible with TI’s SN74ALS632A thru SN74ALS635 series System Environment TL F 8535 – 1 TRI-STATE is a registered trademark of National Semiconductor Corp C1995 National Semiconductor Corporation TL F 8535 RRD-B30M105 Printed in U S A 1 page Memory Read Cycle (Error Detection 1) Single data bit errors cause 3 or 5 bits in the syndrome word to go low The columns of the check bit syndrome matrix (TABLE II) are the syndrome words for all single bit data errors in the 32 bit word (also see TABLE V) The data bit in error corresponds to the column in the check bit syndrome matrix that matches the syndrome word For instance the syndrome word indicating that data bit 31 is in error would be (CB6-CB0) e ‘‘0001010’’ see the column for data bit 31 in TABLE II or see TABLE V During mode 3 (S0 e S1 e 1) the syndrome word is decoded during single data bit errors and used to invert the bit in error thus correcting the data word The correct- ed word is made available on the data I O port (DB0 thru DB31) the check word I O port (CB0 thru CB6) presents the 7-bit syndrome error code This syndrome error code can be used to locate the bad memory chip Correction Details) (Continued) 2) A single check bit error will cause that particular check bit to go low in the syndrome word 3) A double bit error will cause an even number of bits in the syndrome word to go low The syndrome word will then be the EXCLUSIVE NOR of the two individual syndrome words corresponding to the 2 bits in error The two-bit error is not correctable since the parity tree can only identify single bit errors If any of the bits in the syndrome word are low the ‘‘ERR’’ flag goes low The ‘‘MERR’’ (dual error) flag goes low during any double bit error conditions (See Table III) Three or more simultaneous bit errors can cause the EDAC to believe that no error a correctable error or an uncorrect- able error has occurred and will produce erroneous results in all three cases It should be noted that the gross-error conditions of all lows and all highs will be detected TABLE V Syndrome Decoding Syndrome Bits Error 654 3 2 1 0 L L L L L L L unc L L L L L L H 2-bit L L L L L H L 2-bit L L L L L H H unc LL L LL L LL L LL L LHL L LHLH L HH L L HHH 2-bit unc unc 2-bit L L L H L L L 2-bit L L L H L L H unc L L L H L H L DB31 L L L H L H H 2-bit L L L H H L L unc L L L H H L H 2-bit L L L H H H L 2-bit L L L H H H H DB30 L L H L L L L 2-bit L L H L L L H unc L L H L L H L DB29 L L H L L H H 2-bit L L H L H L L DB28 L L H L H L H 2-bit L L H L H H L 2-bit L L H L H H H DB27 L L H H L L L DB26 L L H H L L H 2-bit L L H H L H L 2-bit L L H H L H H DB25 L L H H H L L 2-bit L L H H H L H DB24 L L H H H H L unc L L H H H H H 2-bit CB X e error in check bit X DB Y e error in data bit Y 2-bit e double-bit error unc e uncorrectable multibit error Syndrome Bits Error 65 4 3 2 1 0 L H L L L L L 2-bit L H L L L L H unc L H L L L H L DB7 L H L L L H H 2-bit L H L L H L L DB6 L H L L H L H 2-bit L H L L H H L 2-bit L H L L H H H DB5 L H L H L L L DB4 L H L H L L H 2-bit L H L H L H L 2-bit L H L H L H H DB3 L H L H H L L 2-bit L H L H H L H DB2 L H L H H H L unc L H L H H H H 2-bit L H H L L L L DB0 L H H L L L H 2-bit L H H L L H L 2-bit L H H L L H H unc LHHLHL L LHH L H L H LHH L HH L LHH L HHH 2-bit DB1 unc 2-bit L H H H L L L 2-bit L H H H L L H unc L H H H L H L unc L H H H L H H 2-bit LHHHHL L LHHHH L H LHHHHH L LHHHHHH unc 2-bit 2-bit CB6 Syndrome Bits Error 654 3 2 1 0 H L L L L L L 2-bit H L L L L L H unc H L L L L H L unc H L L L L H H 2-bit HL L HL L HL L HL L LHL L LHLH L HH L L HHH unc 2-bit 2-bit unc H L L H L L L unc H L L H L L H 2-bit H L L H L H L 2-bit H L L H L H H DB15 H L L H H L L 2-bit H L L H H L H unc H L L H H H L DB14 H L L H H H H 2-bit H L H L L L L unc H L H L L L H 2-bit H L H L L H L 2-bit H L H L L H H DB13 H L H L H L L 2-bit H L H L H L H DB12 H L H L H H L DB11 H L H L H H H 2-bit H L H H L L L 2-bit H L H H L L H DB10 H L H H L H L DB9 H L H H L H H 2-bit HLHHHL L HLHHH L H HLHHHH L HLHHHHH DB8 2-bit 2-bit CB5 Syndrome Bits Error 6543210 H H L L L L L unc H H L L L L H 2-bit H H L L L H L 2-bit H H L L L H H DB23 H H L L H L L 2-bit H H L L H L H DB22 H H L L H H L DB21 H H L L H H H 2-bit H H L H L L L 2-bit H H L H L L H DB20 H H L H L H L DB19 H H L H L H H 2-bit H H L H H L L DB18 H H L H H L H 2-bit H H L H H H L 2-bit H H L H H H H CB4 H H H L L L L 2-bit H H H L L L H DB16 H H H L L H L unc H H H L L H H 2-bit H H H L H L L DB17 H H H L H L H 2-bit H H H L H H L 2-bit H H H L H H H CB3 HHHHL L L HHHHL LH HHHH L H L HHHH L HH unc 2-bit 2-bit CB2 H H H H H L L 2-bit H H H H H L H CB1 H H H H H H L CB0 H H H H H H H none 5 5 Page DP8402A DP8404 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range (unless otherwise noted) Symbol VIK VOH VOL II IIH IIL IO ICC Parameter All outputs DB or CB ERR or MERR DB or CB S0 or S1 All others S0 or S1 All others S0 or S1 All others Test Conditions VCC e 4 5V II e b18 mA VCC e 4 5V to 5 5V IOH e b 0 4 mA VCC e 4 5V IOH e b1 mA VCC e 4 5V IOH e b2 6 mA VCC e 4 5V IOL e 4 mA VCC e 4 5V IOL e 8 mA VCC e 4 5V IOL e 12 mA VCC e 4 5V IOL e 24 mA VCC e 5 5V VI e 7V VCC e 5 5V VI e 5 5V VCC e 5 5V VI e 2 7V VCC e 5 5V VI e 0 4V VCC e 5 5V VO e 2 25V VCC e 5 5V (See Note 1) Military Min Typ VCCb2 24 33 0 25 0 25 b30 150 Max b1 5 04 04 01 01 20 20 b0 4 b0 1 b112 250 Commercial Min Typ Max b1 5 VCCb2 24 b30 32 0 25 0 35 0 25 0 35 150 04 05 04 05 01 01 20 20 b0 4 b0 1 b112 250 Units V V V mA mA mA mA mA DP8403 DP8405 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range (unless otherwise noted) Symbol Parameter Test Conditions Military Min Typ Max Commercial Min Typ Max VIK VOH IOH VOL II IIH ERR or MERR DB or CB ERR or MERR DB or CB S0 or S1 All others S0 or S1 All others VCC e 4 5V II e b18 mA VCC e 4 5V to 5 5V IOH e b0 4 mA VCC e 4 5V VOH e 5 5V VCC e 4 5V IOL e 4 mA VCC e 4 5V IOL e 8 mA VCC e 4 5V IOL e 12 mA VCC e 4 5V IOL e 24 mA VCC e 5 5V VI e 7V VCC e 5 5V VI e 5 5V VCC e 5 5V VI e 2 7V VCCb2 0 25 0 25 b1 5 01 04 VCCb2 04 0 25 0 35 0 25 0 35 b1 5 01 04 05 04 05 S0 or S1 IIL VCC e 5 5V VI e 0 4V All others IO ERR or MERR VCC e 5 5V VO e 2 25V b30 b112 b30 b112 ICC VCC e 5 5V (See Note 1) 150 150 All typical values are at VCC e 5V TA e a25 C For I O ports (QA through QH) the parameters IIH and IIL include the off-state output current The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current IOS Note 1 ICC is measured with S0 and S1 at 4 5V and all CB and DB pins grounded Units V V mA V mA mA mA mA mA 11 11 Page

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