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AT89LP51ID2 Schematic ( Datenblatt PDF ) - ATMEL

Teilenummer AT89LP51ID2
Beschreibung 8-bit Microcontroller
Hersteller ATMEL
Logo ATMEL Logo 

Gesamt 26 Seiten
		
AT89LP51ID2 Datasheet, Funktion
Features
8-bit Microcontroller Compatible with 8051 Products
Enhanced 8051 Architecture
– Single Clock Cycle per Byte Fetch
– 12 Clock per Machine Cycle Compatibility Mode
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 16x16 Multiply–Accumulate Unit
– 256 x 8 Internal RAM
– On-chip 2KB Expanded RAM (ERAM)
• Software Selectable Size (0, 256, 512, 768, 1024, 1792, 2048 Bytes)
– Dual Data Pointers
– 4-level Interrupt Priority
Nonvolatile Program and Data Memory
– 64KB of In-System Programmable (ISP) Flash Program Memory
– 4KB of EEPROM (AT89LP51ED2/ID2 Only)
– 512-byte User Signature Array
– Endurance: 10,000 Write/Erase Cycles
– Serial Interface for Program Downloading
– 2KB Boot ROM Contains Low Level Flash Programming Routines and a Default
Serial Bootloader
Peripheral Features
– Three 16-bit Enhanced Timer/Counters
– Seven 8-bit PWM Outputs
– 16-bit Programmable Counter Array
• High Speed Output, Compare/Capture
• Pulse Width Modulation, Watchdog Timer Capabilities
– Enhanced UART with Automatic Address Recognition and Framing
Error Detection
– Enhanced Master/Slave SPI with Double-buffered Send/Receive
– Two Wire Interface 400K bit/s
– Programmable Watchdog Timer with Software Reset
– 8 General-purpose Interrupt and Keyboard Interface Pins
Special Microcontroller Features
– Dual Oscillator Support: Crystal, 32 kHz Crystal, 8 MHz Internal (AT89LP51ID2)
– Two-wire On-Chip Debug Interface
– Brown-out Detection and Power-on Reset with Power-off Flag
– Selectable Polarity External Reset Pin
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
– 8-bit Clock Prescaler
I/O and Packages
– Up to 40 Programmable I/O Lines
– Green (Pb/Halide-free) PLCC44, VQFP44, QFN44, PDIP40
– Configurable I/O Modes
• Quasi-bidirectional (80C51 Style), Input-only (Tristate)
• Push-pull CMOS Output, Open-drain
Operating Conditions
– 2.4V to 5.5V VCC Voltage Range
– -40° C to 85°C Temperature Range
– 0 to 20 MHz @ 2.4V–5.5V (Single-cycle)
8-bit Flash
Microcontroller
with 64KB
Program
Memory
AT89LP51RD2
AT89LP51ED2
AT89LP51ID2
Preliminary
Summary
3714AS–MICRO–7/11






AT89LP51ID2 Datasheet, Funktion
AT89LP51RD2/ED2/ID2 also includes a compatibility mode that will enable classic 12 clock per
machine cycle operation for true timing compatibility with the Atmel AT89C51RD2/ED2.
The AT89LP51RD2/ED2/ID2 retains all of the standard features of the AT89C51RD2/ED2,
including: 64KB of In-System Programmable Flash program memory, 4KB of EEPROM
(AT89LP51ED2/ID2 Only), 256 bytes of RAM, 2KB of expanded RAM, up to 40 I/O lines, three
16-bit timer/counters, a Programmable Counter Array, a programmable hardware watchdog
timer, a keyboard interface, a full-duplex enhanced serial port, a serial peripheral interface (SPI),
on-chip crystal oscillator, and a four-level, ten-vector interrupt system. A block diagram is shown
in Figure 2-1.
In addition, the Atmel® AT89LP51RD2/ED2/ID2 provides a Two-Wire Interface (TWI) for up to
400KB/s serial transfer; a 10-bit, 8-channel Analog-to-Digital Converter (ADC) with temperature
sensor and digital-to-analog (DAC) mode; two analog comparators; an 8MHz internal oscillator;
and more on-chip data memory than the Atmel AT89C51RD2/ED2 (4KB vs. 2KB EEPROM and
2048 vs. 1792 bytes ERAM).
Some standard features on the AT89LP51RD2/ED2/ID2 are enhanced with new modes or oper-
ations. Mode 0 of Timer 0 or Timer 1 acts as a variable 9–16 bit timer/counter and Mode 1 acts
as a 16-bit auto-reload timer/counter. In addition, each timer/counter may independently drive an
8-bit precision pulse width modulation output. Mode 0 (synchronous mode) of the serial port
allows flexibility in the phase/polarity relationship between clock and data.
The I/O ports of the AT89LP51RD2/ED2/ID2 can be independently configured in one of four
operating modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input-
only mode, the ports are tristated. Push-pull output mode provides full CMOS drivers and open-
drain mode provides just a pull-down. Unlike other 8051s, this allows Port 0 to operate with on-
chip pull-ups if desired.
The AT89LP51RD2/ED2/ID2 includes an On-Chip Debug (OCD) interface that allows read-mod-
ify-write capabilities of the system state and program flow control, and programming of the
internal memories. The on-chip Flash and EEPROM may also be programmed through the
UART-based bootloader or the SPI-based In-System programming interface (ISP).
The TWI and OCD features are not available on the PDIP package. The AT89LP51ID2 is also
not available in PDIP.
The features of the AT89LP51RD2/ED2/ID2 make it a powerful choice for applications that need
pulse width modulation, high speed I/O, and counting capabilities such as alarms, motor control,
corded phones, and smart card readers.
6 AT89LP51RD2/ED2/ID2 Summary - Preliminary
3714AS–MICRO–7/11

6 Page







AT89LP51ID2 pdf, datenblatt
3. Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in
Table 3-1.
Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-
mented on the chip. Read accesses to these addresses will in general return random data, and
write accesses will have an indeterminate effect. User software should not write to these unlisted
locations, since they may be used in future products to invoke new features.
Table 3-1. Atmel AT89LP51RD2/ED2/ID2 SFR Map and Reset Values
8 9 ABCDE F
0F8H
CH CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0F0H
B
0000 0000
RL0
RL1
RH0
RH1
PAGE
BX
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0E8H
CL
CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L
SPX
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx x000
0E0H
ACC
0000 0000
AX
0000 0000
DSPR
0000 0000
FIRD
0000 0000
MACL
0000 0000
MACH
0000 0000
P0M0
(2)
P0M1
0000 0000
0D8H
CCON
00x0 0000
CMOD
00xx x000
CCAPM0
x000 0000
CCAPM1
x000 0000
CCAPM2
x000 0000
CCAPM3
x000 0000
CCAPM4
x000 0000
0D0H
PSW
0000 0000
FCON
xxxx 0000
EECON
0000 0000
DPLB
DPHB
0000 0000 0000 0000
P1M0
(2)
P1M1
0000 0000
0C8H T2CON
T2MOD
RCAP2L RCAP2H
TL2
TH2
0000 0000 0000 0000 0000 000 0000 0000 0000 000 0000 0000
P2M0
(2)
P2M1
0000 0000
0C0H
P4
1111 1111
SPCON
SPSTA
SPDAT
0001 0100 0000 0000 xxxx xxxx
P3M0
(2)
P3M1
0000 0000
0B8H
IPL0
xx00 0000
SADEN
0000 0000
AREF
0000 0000
P4M0
(2)
P4M1
0000 0000
0B0H
P3
1111 1111
IEN1
xxxx 0000
IPL1
xxxx 0000
IPH1
xxxx 0000
IPH0
xx00 0000
0A8H
IEN0
0x00 0000
SADDR
0000 0000
ACSRB
DADL
DADH
CLKREG CKCON1
0000 0000 0000 0000 0000 0000 0101 xxxx xxxx xxx0
0A0H
P2
DPCF
AUXR1
ACSRA
DADC
DADI
WDTRST WDTPRG
1111 1111 0000 0000 0000 00x0 0000 0000 0000 0000 0000 0000 (write-only) 0000 0xx0
98H
SCON
0000 0000
SBUF
xxxx xxxx
BRL
BDRCON
KBLS
KBE
KBF KBMOD
0000 0000 xxx0 0000 0000 0000 0000 0000 0000 0000 0000 0000
90H
P1
1111 1111
TCONB
0010 0100
BMSEL
xxxx xxx0
SSCON
0000 0000
SSCS
1111 1000
SSDAT
SSADR
1111 1111 1111 1110
CKRL
1111 1111
88H
TCON
0000 0000
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
TH0
0000 0000
TH1
0000 0000
AUXR
0000 0000
CKCON0
0000 0000
80H
P0
1111 1111
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
CKSEL OSCCON
PCON
xxxx xxx0 xxxx x001 000x 0000
Notes:
0123456
1. All SFRs in the left-most column are bit-addressable.
2. Reset value is 1111 1111B when Tristate-Port Fuse is enabled and 0000 0000B when disabled.
3. Reset value is 0101 0010B when Compatibility mode is enabled and 0000 0000B when disabled.
7
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
97H
8FH
87H
12 AT89LP51RD2/ED2/ID2 Summary - Preliminary
3714AS–MICRO–7/11

12 Page


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