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AT89LP51 Schematic ( Datenblatt PDF ) - ATMEL

Teilenummer AT89LP51
Beschreibung 8-bit Microcontroller
Hersteller ATMEL
Logo ATMEL Logo 

Gesamt 30 Seiten
		
AT89LP51 Datasheet, Funktion
Features
8-bit Microcontroller Compatible with 8051 Products
Enhanced 8051 Architecture
– Single Clock Cycle per Byte Fetch
– 12 Clock per Machine Cycle Compatibility Mode
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 256 x 8 Internal RAM
– External Data/Program Memory Interface
– Dual Data Pointers
– 4-level Interrupt Priority
Nonvolatile Program and Data Memory
– 4K/8K Bytes of In-System Programmable (ISP) Flash Program Memory
– 256 Bytes of Flash Data Memory
– 256-byte User Signature Array
– Endurance: 10,000 Write/Erase Cycles
– Serial Interface for Program Downloading
– 64-byte Fast Page Programming Mode
– 3-level Program Memory Lock for Software Security
– In-Application Programming of Program Memory
Peripheral Features
– Three 16-bit Timer/Counters with Clock Out Modes
– Enhanced UART
• Automatic Address Recognition
• Framing Error Detection
• SPI and TWI Emulation Modes
– Programmable Watchdog Timer with Software Reset and Prescaler
Special Microcontroller Features
– Brown-out Detection and Power-on Reset with Power-off Flag
– Selectable Polarity External Reset Pin
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
– Internal 1.8432 MHz Auxiliary Oscillator
I/O and Packages
– Up to 36 Programmable I/O Lines
– Green (Pb/Halide-free) Packages
• 40-lead PDIP
• 44-lead TQFP/PLCC
• 44-pad VQFN/MLF
– Configurable Port Modes (per 8-bit port)
• Quasi-bidirectional (80C51 Style)
• Input-only (Tristate)
• Push-pull CMOS Output
• Open-drain
Operating Conditions
– 2.4V to 5.5V VCC Voltage Range
– -40° C to 85°C Temperature Range
– 0 to 20 MHz @ 2.4V–5.5V
– 0 to 25 MHz @ 4.5V–5.5V
8-bit
Microcontroller
with 4K/8K
Bytes In-System
Programmable
Flash
AT89LP51
AT89LP52
3709D–MICRO–12/11






AT89LP51 Datasheet, Funktion
2. Overview
The AT89LP51/52 is a low-power, high-performance CMOS 8-bit microcontroller with 4K/8K
bytes of In-System Programmable Flash program memory and 256 bytes of Flash data memory.
The device is manufactured using Atmel's high-density nonvolatile memory technology and is
compatible with the industry-standard 80C52 instruction set.
The AT89LP51/52 is built around an enhanced CPU core that can fetch a single byte from mem-
ory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing
instructions to execute in 12, 24 or 48 clock cycles. In the AT89LP51/52 CPU, instructions need
only 1 to 4 clock cycles providing 6 to 12 times more throughput than the standard 8051. Sev-
enty percent of instructions need only as many clock cycles as they have bytes to execute, and
most of the remaining instructions require only one additional clock. The enhanced CPU core is
capable of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the
same current consumption. Conversely, at the same throughput as the classic 8051, the new
CPU core runs at a much lower speed and thereby greatly reducing power consumption and
EMI. The AT89LP51/52 also includes a compatibility mode that will enable classic 12 clock per
machine cycle operation for true timing compatibility with AT89S51/52.
The AT89LP51/52 provides the following standard features: 4K/8K bytes of In-System
Programmable Flash program memory, 256 bytes of Flash data memory, 256 bytes of RAM, up
to 36 I/O lines, three 16-bit timer/counters, a programmable watchdog timer, a full-duplex serial
port, an on-chip crystal oscillator, an internal 1.8432 MHz auxiliary oscillator, and a four-level,
six-vector interrupt system. A block diagram is shown in Figure 2-1.
Key Benefits:
• Full software and timing compatibility with AT89S52 means no changes to existing software,
including fetching from external ROM or read/write from/to external RAM
• Disable compatibility mode to achieve on average 9 times more throughput at the same
current consumption and frequency as AT89S52; or lower the clock frequency 9 times and
achieve the same speed as AT89S52 but with more than 5 times less current consumption
Save even more power and the cost of a quartz crystal by using the internal 1.8432 MHz RC
oscillator, which is Vcc and temperature compensated well enough to ensure proper UART
serial communications. Together with the built-in POR and the BOD circuits, you do not need
any external components for AT89LP52 to provide the reset and clock functions
• All three timer/counters of the AT89LP51/52, Timer 0, Timer 1 and Timer 2, can be
configured to toggle a port pin on overflow for clock/waveform generation. Unlike AT89S51,
Timer 2 is also present on AT89LP51
• The enhanced full-duplex UART of the AT89LP51/52 includes Framing Error Detection and
Automatic Address Recognition. In addition, enhancements to Mode 0 allow hardware
accelerated emulation of a master SPI or TWI
• Use In-Application Programming to alter the built-in 8K Flash program memory while
executing the application, in effect making it possible to have programmable data tables
embedded in the program code. Or use the 256-byte Flash Data memory for nonvolatile data
storage
• Each 8-bit I/O port of the AT89LP51/52 can be independently configured in one of four
operating modes. In quasi-bidirectional mode, the port operates as in the classic 8051. In
input-only mode, the port is tristated. Push-pull output mode provides full CMOS drivers and
open-drain mode provides just a pull-down. Unlike other 8051s, this allows Port 0 to operate
with on-chip pull-ups if desired
6 AT89LP51/52
3709D–MICRO–12/11

6 Page







AT89LP51 pdf, datenblatt
3.1.1
Figure 3-1. Program Memory Map
01FF
0100
AT89LP51
User Signature Array
007F
0000
Atmel Signature Array
FFFF
01FF
0100
007F
0000
FFFF
AT89LP52
User Signature Array
Atmel Signature Array
SIGEN=1
External Program
Memory
(XCODE: 60KB)
1000
0FFF
0000
Internal Program
Memory
(CODE: 4KB)
2000
1FFF
0000
External Program
Memory
(XCODE: 56KB)
Internal Program
Memory
(CODE: 8KB)
SIGEN=0
External Program Memory Interface
The AT89LP51/52 uses the standard 8051 external program memory interface with the upper
address on Port 2, the lower address and data in/out multiplexed on Port 0, and the ALE and
PSEN strobes. Program memory addresses are always 16-bits wide, even though the actual
amount of program memory used may be less than 64K byes. External program execution sacri-
fices two full 8-bit ports, P0 and P2, to the function of addressing the program memory.
Figure 3-2 shows a hardware configuration for accessing up to 64K bytes of external ROM using
a 16-bit linear address. Port 0 serves as a multiplexed address/data bus to the ROM. The
Address Latch Enable strobe (ALE) is used to latch the lower address byte into an external reg-
ister so that Port 0 can be freed for data input/output. Port 2 provides the upper address byte
throughout the operation. PSEN strobes the external memory.
Figure 3-3 shows the timing of the external program memory interface. ALE is emitted at a con-
stant rate of 1/3 of the system clock with a 1/3 duty cycle. PSEN is emitted at a similar rate, but
with 50% duty cycle. The new address changes in the middle of the ALE pulse for latching on
the falling edge and is tristated at the falling edge of PSEN. The instruction data is sampled from
P0 and latched internally during the high phase of the clock prior to the rising edge of PSEN.
This timing applies to both Compatibility and Fast modes. In Compatibility mode there is no dif-
ference in instruction timing between internal and external execution.
Figure 3-2. Executing from External Program Memory
AT89LP
P1 P0
EXTERNAL
PROGRAM
MEMORY
INSTR.
ALE
P3 P2
PSEN
LATCH
ADDR
OE
12 AT89LP51/52
3709D–MICRO–12/11

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