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AT89LP3240 Schematic ( Datenblatt PDF ) - ATMEL

Teilenummer AT89LP3240
Beschreibung 8-bit Microcontroller
Hersteller ATMEL
Logo ATMEL Logo 

Gesamt 30 Seiten
		
AT89LP3240 Datasheet, Funktion
Features
8-bit Microcontroller Compatible with MCS®51 Products
Enhanced 8051 Architecture
– Single-clock Cycle per Byte Fetch
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 16x16 Multiply–Accumulate Unit
– 256x8 Internal RAM
– 4096x8 Internal Extra RAM
– Up to 4KB Extended Stack in Extra RAM
– Dual Data Pointers
– 4-level Interrupt Priority
Nonvolatile Program and Data Memory
– 32K/64K Bytes of In-System Programmable (ISP) Flash Program Memory
– 8K Bytes of Flash Data Memory
– Endurance: Minimum 100,000 Write/Erase Cycles
– Serial Interface for Program Downloading
– 64-byte Fast Page Programming Mode
– 256-Byte User Signature Array
– 2-level Program Memory Lock for Software Security
– In-Application Programming of Program Memory
Peripheral Features
– Three 16-bit Enhanced Timer/Counters
– Two 8-bit PWM Outputs
– 4-Channel 16-bit Compare/Capture/PWM Array
– Enhanced UART with Automatic Address Recognition and Framing
Error Detection
– Enhanced Master/Slave SPI with Double-buffered Send/Receive
– Master/Slave Two-Wire Serial Interface
– Programmable Watchdog Timer with Software Reset
– Dual Analog Comparators with Selectable Interrupts and Debouncing
– 8-channel 10-bit ADC/DAC
– 8 General-purpose Interrupt Pins
Special Microcontroller Features
– Two-wire On-chip Debug Interface
– Brown-out Detection and Power-on Reset with Power-off Flag
– Active-low External Reset Pin
– Internal RC Oscillator
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
I/O and Packages
– Up to 38 Programmable I/O Lines
– 40-lead PDIP or 44-lead TQFP/PLCC or 44-pad VQFN/MLF
– Configurable I/O Modes
• Quasi-bidirectional (80C51 Style)
• Input-Only (Tristate)
• Push-pull CMOS Output
• Open-drain
Operating Conditions
– 2.4V to 3.6V VDD Voltage Range
– -40° C to 85°C Temperature Range
– 0 to 20 MHz @ 2.4–3.6V
8-bit
Microcontroller
with 32K/64K
Bytes In-System
Programmable
Flash
AT89LP3240
AT89LP6440
3706C–MICRO–2/11






AT89LP3240 Datasheet, Funktion
Table 1-1. AT89LP3240/6440 Pin Description
Pin Number
TQFP PLCC PDIP VQFN Symbol Type
I/O
35 41 37 35 P0.2
O
I
I/O
36 42 38 36 P0.1
O
I
I/O
37 43 39 37 P0.0
O
I
38 44 40 38 VDD
I
39 1
39 VDD
I
40 2
I/O
1 40 P1.0 I/O
I
41 3
I/O
2 41 P1.1
I
I
42 4
3
42
P1.2
I/O
I
43 5
4
43
P1.3
I/O
I
44 6
I/O
5 44 P1.4
I
I
Description
P0.2: User-configurable I/O Port 0 bit 2.
AD2: External memory interface Address/Data bit 2.
ADC2: ADC analog input 2.
P0.1: User-configurable I/O Port 0 bit 1.
AD1: External memory interface Address/Data bit 1.
ADC1: ADC analog input 1.
P0.0: User-configurable I/O Port 0 bit 0.
AD0: External memory interface Address/Data bit 0.
ADC0: ADC analog input 0.
Supply Voltage
Supply Voltage
P1.0: User-configurable I/O Port 1 bit 0.
T2: Timer 2 External Input or Clock Output.
GPI0: General-purpose Interrupt input 0.
P1.1: User-configurable I/O Port 1 bit 1.
T2EX: Timer 2 External Capture/Reload Input.
GPI1: General-purpose Interrupt input 1
P1.2: User-configurable I/O Port 1 bit 2.
GPI2: General-purpose Interrupt input 2.
P1.3: User-configurable I/O Port 1 bit 3.
GPI3: General-purpose Interrupt input 3.
P1.4: User-configurable I/O Port 1 bit 4.
SS: SPI Slave-Select.
GPI6: General-purpose Interrupt input 4.
2. Overview
The AT89LP3240/6440 is a low-power, high-performance CMOS 8-bit microcontroller with
32K/64K bytes of In-System Programmable Flash program memory and 8K bytes of Flash data
memory. The device is manufactured using Atmel®'s high-density nonvolatile memory technol-
ogy and is compatible with the industry-standard 8051 instruction set. The AT89LP3240/6440 is
built around an enhanced CPU core that can fetch a single byte from memory every clock cycle.
In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instructions to exe-
cute in 12, 24 or 48 clock cycles. In the AT89LP3240/6440 CPU, standard instructions need only
1 to 4 clock cycles providing 6 to 12 times more throughput than the standard 8051. Seventy
percent of instructions need only as many clock cycles as they have bytes to execute, and most
of the remaining instructions require only one additional clock. The enhanced CPU core is capa-
ble of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same
current consumption. Conversely, at the same throughput as the classic 8051, the new CPU
core runs at a much lower speed and thereby greatly reducing power consumption and EMI.
The AT89LP3240/6440 provides the following standard features: 32K/64K bytes of In-System
Programmable Flash program memory, 8K bytes of Flash data memory, 4352 bytes of RAM, up
to 38 I/O lines, three 16-bit timer/counters, up to six PWM outputs, a programmable watchdog
timer, two analog comparators, a 10-bit ADC/DAC with 8 input channels, a full-duplex serial port,
a serial peripheral interface, a two-wire serial interface, an internal RC oscillator, on-chip crystal
oscillator, and a four-level, twelve-vector interrupt system. A block diagram is shown in Figure 2-
1.
6 AT89LP3240/6440
3706C–MICRO–2/11

6 Page







AT89LP3240 pdf, datenblatt
Figure 3-1.
01FF
0100
007F
0000
Program Memory Map
AT89LP3240
User Signature Array
Atmel Signature Array
01FF
0100
007F
0000
FFFF
AT89LP6440
User Signature Array
Atmel Signature Array
SIGEN=1
7FFF
Program Memory
Program Memory
SIGEN=0
0000
0000
3.2 Internal Data Memory
The AT89LP3240/6440 contains 256 bytes of general SRAM data memory plus 128 bytes of I/O
memory mapped into a single 8-bit address space. Access to the internal data memory does not
require any configuration. The internal data memory has three address spaces: DATA, IDATA
and SFR; as shown in Figure 3-2. Some portions of external data memory are also implemented
internally. See “External Data Memory” below for more information.
3.2.1 DATA
Figure 3-2. Internal Data Memory Map
FFH
UPPER
128
80H
7FH
LOWER
128
IDATA
ACCESSIBLE
BY INDIRECT
ADDRESSING
ONLY
DATA/IDATA
ACCESSIBLE
BY DIRECT
AND INDIRECT
ADDRESSING
0
SFR
ACCESSIBLE
BY DIRECT
ADDRESSING
FFH
80H
SPECIAL
FUNCTION
REGISTERS
PORTS
STATUS AND
CONTROL BITS
TIMERS
REGISTERS
STACK POINTER
ACCUMULATOR
(ETC.)
The first 128 bytes of RAM are directly addressable by an 8-bit address (00H–7FH) included in
the instruction. The lowest 32 bytes of DATA memory are grouped into 4 banks of 8 registers
each. The RS0 and RS1 bits (PSW.3 and PSW.4) select which register bank is in use. Instruc-
tions using register addressing will only access the currently specified bank. The lower 128 bit
addresses are also mapped into DATA addresses 20H—2FH.
12 AT89LP3240/6440
3706C–MICRO–2/11

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