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GS9025ACQME3 Schematic ( PDF Datasheet ) - GENNUM

Teilenummer GS9025ACQME3
Beschreibung Serial Digital Receiver
Hersteller GENNUM
Logo GENNUM Logo 




Gesamt 18 Seiten
GS9025ACQME3 Datasheet, Funktion
GENLINX II GS9025A
Serial Digital Receiver
FEATURES
• SMPTE 259M compliant
• operational to 540Mb/s
• automatic cable equalization (typically greater than
350m of high quality cable at 270Mb/s)
• adjustment-free operation
• auto-rate selection (5 rates) with manual override
• single external VCO resistor for operation with five
input data rates
• data rate indication output
• serial data outputs muted and serial clock remains
active when input data is lost
• operation independent of SAV/EAV sync signals
• signal strength indicator output
• carrier detect with programmable threshold level
• power savings mode (output serial clock disable)
• Pb-free and Green
APPLICATIONS
Cable equalization plus clock and data recovery for all high
speed serial digital interface applications involving SMPTE
259M and other data standards.
DATA SHEET
DESCRIPTION
The GS9025A provides automatic cable equalization and
high performance clock and data recovery for serial digital
signals. The GS9025A receives either single-ended or
differential serial digital data and outputs differential clock
and retimed data signals at PECL levels (800mV). The on-
board cable equalizer provides up to 40dB of gain at
200MHz which typically results in equalization of greater
than 350m of high quality cable at 270Mb/s.
The GS9025A operates in either auto or manual data rate
selection mode. In both modes, the GS9025A requires only
one external resistor to set the VCO centre frequency and
provides adjustment free operation.
The GS9025A has dedicated pins to indicate signal
strength/carrier detect, LOCK and data rate. Optional
external resistors allow the carrier detect threshold level to
be customized to the user's requirement. In addition, the
GS9025A provides an 'Output Eye Monitor Test'
(OEM_TEST) for diagnostic testing of signal integrity after
equalization, prior to reslicing. The serial clock outputs can
also be disabled to reduce power. The GS9025A operates
from a single +5 or -5 volt supply.
ORDERING INFORMATION
PART NUMBER
GS9025ACQM
GS9025ACTM
GS9025ACQME3
GS9025ACTME3
PACKAGE
44 pin MQFP Tray
44 pin MQFP Tape
44 pin MQFP Tray
44 pin MQFP Tape
TEMPERATURE
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
Pb-FREE AND GREEN
No
No
Yes
Yes
A/D
DDI
ANALOG
CARRIER DETECT
DDI
DIGITAL
MUX
PHASELOCK
HARMONIC
SDI +
SDI --
VARIABLE
GAIN EQ
STAGE
OEM_TEST
EYE
MONITOR
AUTO EQ
CONTROL
FREQUENCY
ACQUISITION
PHASE
DETECTOR
DIVISION
+-
AGC CAP CD_ADJ
CHARGE
PUMP
VCO
SSI/CD LF+ LFS LF-
CBG RVCO
BLOCK DIAGRAM
COSC
LOGIC MUTE
3 BIT
COUNTER
DECODER
LOCK
SDO
SDO
CLK_EN
SCO
SCO
SMPTE
AUTO/MAN
SS0
SS1
SS2
Revision Date: August 2005
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
Document No. 522 - 75 - 05






GS9025ACQME3 Datasheet, Funktion
PIN DESCRIPTIONS (Continued)
NUMBER
SYMBOL TYPE
DESCRIPTION
28, 29
SCO/SCO
O Serial clock output. SCO/SCO are differential current mode outputs and require
external 75Ω pull-up resistors.
31, 32
SDO/SDO
O Equalized and reclocked serial digital data outputs. SDO/SDO are differential current
mode outputs and require external 75Ω pull-up resistors.
36
CLK_EN
I Clock enable. When HIGH, the serial clock outputs are enabled.
38
COSC
I Timing control capacitor for internal system clock.
39
LOCK
O Lock indication. When HIGH, the GS9025A is locked. LOCK is an open collector output
and requires an external 10kΩ pull-up resistor.
40
SSI/CD
O Signal strength indicator/Carrier detect.
41 A/D I Analog/Digital select.
42
SMPTE
I SMPTE/Other data rate select. TTL/CMOS compatible input.
43
OEM_TEST
O Output ‘Eye’ monitor test. Single-ended current mode output that requires an external
50Ω pull-up resistor. This feature is recommended for debugging purposes only. If
enabled during normal operation, the maximum operating temperature is rated to
60°C. For maximum cable length performance OEM_TEST must be disabled.
GENNUM CORPORATION
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GS9025ACQME3 pdf, datenblatt
2.3 Logic Circuit
The GS9025A is controlled by a finite state logic circuit
which is clocked by an asynchronous system clock. In other
words, the system clock is completely independent of the
incoming data rate. It runs at low frequencies, relative to the
incoming data rate, thereby reducing interference to the
PLL. The period of the system clock is set by the COSC
capacitor and is
tsys = 9.6 × 104 × COSC[ sec onds]
The recommended value for tsys is 450µs (COSC = 4.7nF).
2.4 Auto/Manual Data Rate Select
The GS9025A can operate in either auto or manual data
rate select mode. The mode of operation is selected by a
single input pin (AUTO/MAN).
2.4.1 Auto Mode (AUTO/MAN = 1)
In auto mode, the GS9025A uses a 3-bit counter to
automatically cycle through five (SMPTE=1) or three
(SMPTE=0) different divider moduli as it attempts to acquire
lock. In this mode, the SS[2:0] pins are outputs and indicate
the current value of the divider moduli according to Table 2.
NOTE: For SMPTE = 0 and divider moduli of 2 and 4, the
PLL can correctly lock for two values of SS[2:0].
TABLE 2.
AUTO/MAN = 1 (AUTO MODE)
ƒH, ƒL = VCO centre frequency as per Figure 19.
SMPTE
SS[2:0]
DIVIDER
MODULI
1 000 4
1 001 2
1 010 2
1 011 1
1 100 1
1 101 -
1 110 -
1 111 -
0 000 4
0 001 4
0 010 2
0 011 2
0 100 1
0 101 -
0 110 -
0 111 -
PLL CLOCK
ƒH/4
ƒL/2
ƒH/2
ƒL
ƒH
-
-
-
ƒH/4
ƒH/4
ƒH/2
ƒH/2
ƒH
-
-
-
2.4.2 Manual Mode (AUTO/MAN = 0)
In manual mode, the GS9025A divider moduli is fixed. In
this mode, the SS[2:0] pins are inputs and set the divider
moduli according to Table 3.
TABLE 3.
AUTO/MAN = 1 (MANUAL MODE)
ƒH, ƒL = VCO centre frequency as per Figure 19.
SMPTE
SS[2:0]
DIVIDER
MODULI
1 000 4
1 001 2
1 010 2
1 011 1
1 100 1
1 101 8
1 110 8
1 111 -
0 000 4
0 001 4
0 010 2
0 011 2
0 100 1
0 101 1
0 110 8
0 111 -
PLL CLOCK
ƒH/4
ƒL/2
ƒH/2
ƒL
ƒH
ƒL/8
ƒH/8
-
ƒH/4
ƒH/4
ƒH/2
ƒH/2
ƒH
ƒH
ƒH/8
-
2.5 LOCKING
The GS9025A indicates lock when three conditions are
satisfied:
1. Input data is detected.
2. The incoming data signal and the PLL clock are phase
locked.
3. The system is not locked to a harmonic.
The GS9025A defines the presence of input data when at
least one data transition occurs every 1µs.
The GS9025A assumes that it is NOT locked to a harmonic
if the pattern ‘101’ or ‘010’ (in the reclocked data stream)
occurs at least once every tsys/3 seconds. Using the
recommended component values, this corresponds to
approximately 150µs. In a harmonically locked system, all
bit cells are double clocked and the above patterns
become ‘110011’ and ‘001100’, respectively.
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