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Teilenummer | 82C546 |
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Beschreibung | PYTHON CHIPSET FOR PENTIUM PROCESSORS | |
Hersteller | OPTi | |
Logo | ||
Gesamt 30 Seiten PYTHON CHIPSET
FOR PENTIUM ™
PROCESSORS
May 1994
OPTi Inc.. 2525 Walsh Avenue· Santa Clara, CA 95051 . (408) 980-8178
82C546/82C547
3.1.4.3
3.1.4.4
3.1.4.5
Buffer Control Interface Signals......................................................................................... 31
Miscellaneous Interface Signals .........................................................................,............... 31
Ground and Power Pins ...................................................................................................... 32
4.0 Functional Description...................................................................................................................33
4.1 Reset Logic.......................................................................................................................................................... 33
4.2 System Clocks..................................................................................................................................................... 33
4.2.1 CPU and SYSC Clocks ........................................................................................................................ 33
4.2.2 VL Bus Clocks ..................................................................................................................................... 33
4.2.3 AT Bus Clocks ..................................................................................................................................... 35
4.3 Cache Subsystem................................................................................................................................................ 36
4.3.1 CPU Burst Mode ControL.................................................................................................................... 36
4.3.2 Cache Cycle Types .............................................................................................................................. 36
4.3.3 Cache Operation................................................................................................................................... 37
4.3.3.1 L2 Cache Read-Hit ............................................................................................................. 37
4.3.3.2 L2 Cache Write-Hit Cycle .................................................................................................. 37
4.3.3.3 L2 Cache Read-Miss........................................................................................................... 40
4.3.3.4 L2 Cache Write-Miss.......................................................................................................... 40
4.3.3.5 Tag Compare Table ............................................................................................................ 44
4.3.3.6 Cache Critical Paths............................................................................................................ 44
4.3.3.7 Single Bank Cache Verses Double Bank Cache................................................................. 45
4.3.3.8 Cache Initialization ............................................................................................................. 45
4.3.3.9 Write-Back Cache with DMAIISA MasterNL Master Operations ................................... 45
4.3.3.10 DMAlMaster Write Cycle .................................................................................................. 49
4.3.3.11 Cacheability and Write Protection...................................................................................... 51
4.3.3.12 SRAM Requirements .......................................................................................................... 52
4.4 DRAM Controller .............................................................................................................................................. 53
4.4.1 DRAM Read Cycle .............................................................................................................................. 54
4.4.2 DRAM Write Cycle .........:................................................................................................................... 54
4.4.3 DRAM Parity GenerationIDetection Logic ......................................................................................... 54
4.4.4 DRAM Refresh Logic .......................................................................................................................... 55
4.4.5 DRAM Address Muxing...................................................................................................................... 55
4.4.6 DRAM DMAlMaster Cycles ............................................................................................................... 56
4.5 AT Bus Interface ................................................................................................................................................ 57
4.6 Bus Arbitration Logic........................................................................................................................................ 58
4.7 VL Bus Interface ................................................................................................................................................. 58
4.7.1 VL Bus Slave ....................................................................................................................................... 59
4.7.2 VL Bus Master..................................................................................................................................... 60
[.mil
Pageiv
DBS-Ol-CS002-1.0
Python Chipset
6 Page 82C546/82C547
Table 5-9
Table 5-10
Table 5-11
Table 5-12
Table 5-13
Table 5-14
Table 5-15
Table 5-16
Table 5-17
Table 5-18
Table 5-19
Table 5-20
Tag Test Register: Index 07h ...................................................................................................................... 69
CPU Cache Control Register 1: Index 08h ................................................................................................. 69
System Memory Function Register 1: Index 09h ....................................................................................... 70
System Memory Address Decode Register 1: Index OAb .......................................................................... 70
System Memory Address Decode Register 2: Index OBh........................................................................... 70
Extended DMA Register: Index OCh .......................................................................................................... 70
ROMCS# Register: Index ODh ................................................................................................................... 71
Local Master Preemption Register: Index OEh ........................................................................................... 71
Deturbo Control Register 1: Index OFh....................................................................................................... 72
Cache Write-hit Control Register: Index IOh ............................................................................................. 72
Master Cycle Control Register: Index I Ih.................................................................................................. 73
PS/2 Reset Control: Port 92h ...................................................................................................................... 73
Page x
D85-01·C5002-1.0
Python ChipsEt
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ 82C546 Schematic.PDF ] |
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