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DS2430A Schematic ( PDF Datasheet ) - Maxim Integrated

Teilenummer DS2430A
Beschreibung 256-Bit 1-Wire EEPROM
Hersteller Maxim Integrated
Logo Maxim Integrated Logo 




Gesamt 19 Seiten
DS2430A Datasheet, Funktion
19-5236; Rev 2/12
DS2430A
256-Bit 1-Wire EEPROM
FEATURES
256-bit Electrically Erasable Programmable
Read Only Memory (EEPROM) plus 64-bit
one-time programmable application register
Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-bit
serial number + 8-bit CRC tester) assures
absolute identity because no two parts are alike
Built-in multidrop controller ensures
compatibility with other MicroLAN products
EEPROM organized as one page of 32 bytes
for random access
Reduces control, address, data, and power to a
single data pin
Directly connects to a single port pin of a
microprocessor and communicates at up to
15.3kbits per second
8-bit family code specifies DS2430A
communication requirements to reader
Presence detector acknowledges when reader
first applies voltage
Low cost TO-92 or 6-pin TSOC and UCSP
surface mount package
Reads and writes over a wide voltage range of
2.8V to 5.25V from -40°C to +85°C
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS2430A+
-40°C to +85°C 3 TO-92
DS2430A+T&R -40°C to +85°C 3 TO-92 (2k pcs)
DS2430AP+
-40°C to +85°C 6 TSOC
DS2430AP+T&R -40°C to +85°C 6 TSOC (4k pcs)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
PIN ASSIGNMENT
TO-92
DALLAS
DS2430A
TSOC PACKAGE
16
25
34
TOP VIEW
3.7mm x 4.0mm x 1.5mm
SIDE VIEW
123
12 3
BOTTOM VIEW
NOTE: The leads of TO-92 packages on tape and reel are formed
to approximately 100-mil (2.54mm) spacing. For details see the
Package Information.
PIN DESCRIPTION
TO-92 TSOC
Pin 1 Ground Ground
Pin 2 Data
Data
Pin 3 NC
NC
Pin 4 ––––
NC
Pin 5 ––––
NC
Pin 6 ––––
NC
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DS2430A Datasheet, Funktion
MEMORY FUNCTION FLOW CHART Figure 6
DS2430A
COPY SCRATCHPAD [55h]
After the data stored in the scratchpad has been verified the master may send the Copy Scratchpad
command followed by a validation key of A5h to transfer data from the scratchpad to the EEPROM
memory. This command always copies the data of the entire scratchpad. Therefore, if one desires to
change only a few bytes of the EEPROM data, the scratchpad should contain a copy of the latest
EEPROM data before the Write Scratchpad and Copy Scratchpad commands are issued. After this
command and the validation key are issued, the data line must be held above VPUPmin for at least tPROG.
READ MEMORY [F0h]
The Read Memory command is used to read a portion or all of the EEPROM data memory and to copy
the entire data memory into the scratchpad to prepare for changing a few bytes. To copy data from the
data memory to the scratchpad and to read it, the master must issue the read memory command followed
by the 1-byte starting address of the data to be read from the scratchpad. The DS2430A automatically
increments the address after every byte read by the master. After the data of address 1Fh has been read,
the address counter wraps around to 00h for the next byte and reading continues until the master sends a
Reset Pulse. If one intends to copy the entire data memory to the scratchpad without reading data, a
starting address is not required; the master may send a Reset Pulse immediately following the command
code.
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DS2430A pdf, datenblatt
DS2430A
After one complete pass, the bus master knows the contents of the ROM in one device. The remaining
number of devices and their ROM codes may be identified by additional passes. See Application Note
187 for a comprehensive discussion of a search ROM, including an actual example.
1-Wire Signaling
The DS2430A requires strict protocols to insure data integrity. The protocol consists of four types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write-0, Write-1 and Read-
Data. All these signals (except Presence Pulse) are initiated by the bus master.
To get from idle to active, the voltage on the 1-Wire line needs to fall from VPUP below the threshold VTL.
To get from active to idle, the voltage needs to rise from VILMAX past the threshold VTH. The time it takes
for the voltage to make this rise is seen in Figure 9 as ε, and its duration depends on the pullup resistor
(RPUP) used and the capacitance of the 1-Wire network attached. The voltage VILMAX is relevant for the
DS2430A when determining a logical level, not triggering any events.
Figure 9 shows the initialization sequence required to begin any communication with the DS2430A. A
Reset Pulse followed by a Presence Pulse indicates the DS2430A is ready to receive data, given the
correct ROM and memory function command. If the bus master uses slew-rate control on the falling
edge, it must pull down the line for tRSTL + tF to compensate for the edge.
After the bus master has released the line it goes into Receive mode. Now the 1-Wire bus is pulled to
VPUP through the pullup resistor. When the threshold VTH is crossed, the DS2340A waits for tPDH and then
transmits a Presence Pulse by pulling the line low for tPDL. To detect a Presence Pulse, the master must
test the logical state of the 1-Wire line at tMSP. The tRSTH window must be at least the sum of tPDHMAX,
tPDLMAX, and tRECMIN. Immediately after tRSTH is expired, the DS2430A is ready for data communication.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 9
MASTER TX “RESET PULSE” MASTER RX “PRESENCE PULSE”
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tF
ε tMSP
tRSTL
tPDH
tPDL
tRSTH
tREC
RESISTOR
MASTER
DS2430A
Read/Write Time Slots
Data communication with the DS2430A takes place in time slots, which carry a single bit each. Write
time slots transport data from bus master to slave. Read time slots transfer data from slave to master.
Figure 10 illustrates the definitions of the write and read time slots.
All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line
falls below the threshold VTL, the DS2430A starts its internal timing generator that determines when the
data line is sampled during a write time slot and how long data is valid during a read time slot.
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