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DS2431 Schematic ( PDF Datasheet ) - Maxim Integrated

Teilenummer DS2431
Beschreibung 1-Wire EEPROM
Hersteller Maxim Integrated
Logo Maxim Integrated Logo 




Gesamt 27 Seiten
DS2431 Datasheet, Funktion
DS2431
1024-Bit, 1-Wire EEPROM
General Description
The DS2431 is a 1024-bit, 1-Wire® EEPROM chip orga-
nized as four memory pages of 256 bits each. Data is
written to an 8-byte scratchpad, verified, and then copied
to the EEPROM memory. As a special feature, the four
memory pages can individually be write protected or
put in EPROM-emulation mode, where bits can only be
changed from a 1 to a 0 state. The DS2431 communi-
cates over the single-conductor 1-Wire bus. The com-
munication follows the standard 1-Wire protocol. Each
device has its own unalterable and unique 64-bit ROM
registration number that is factory lasered into the chip.
The registration number is used to address the device in
a multidrop, 1-Wire net environment.
Applications
Accessory/PCB Identification
● Medical Sensor Calibration Data Storage
● Analog Sensor Calibration Including IEEE P1451.4
Smart Sensors
Ink and Toner Print Cartridge Identification
● After-Market Management of Consumables
Typical Operating Circuit
VCC
µC
RPUP
IO
DS2431
GND
Pin Configurations appear at end of data sheet.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
Benefits and Features
● Easily Add Traceability and Relevant Information to
Any Individual System
• 1024 Bits of EEPROM Memory Partitioned Into
Four Pages of 256 Bits
• Individual Memory Pages Can Be Permanently
Write Protected or Put in EPROM-Emulation Mode
(Write to 0)
• Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise
● Minimalist 1-Wire Interface Lowers Cost and
Interface Complexity
• IEC 1000-4-2 Level 4 ESD Protection
(±8kV Contact, ±15kV Air, typ)
• Reads and Writes Over a Wide Voltage Range
from 2.8V to 5.25V from -40°C to +85°C
• Communicates to Host with a Single Digital Signal
at 15.4kbps or 125kbps
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
DS2431+
-40°C to +85°C 3 TO-92
DS2431+T&R
-40°C to +85°C 3 TO-92
DS2431P+
-40°C to +85°C 6 TSOC
DS2431P+T&R -40°C to +85°C 6 TSOC
DS2431G+U
-40°C to +85°C 2 SFN (6mm x 6mm)
DS2431G+T&R
-40°C to +85°C
2 SFN (6mm x 6mm)
(2.5k pcs)
DS2431GA+U
-40°C to +85°C 2 SFN (3.5mm x 6.5mm)
DS2431GA+T&R
-40°C to +85°C
2 SFN (3.5mm x 6.5mm)
(2.5k pcs)
DS2431Q+T&R -40°C to +85°C 6 TDFN-EP* (2.5k pcs)
DS2431X-S+
-40°C to +85°C 3x3 UCSPR (2.5k pcs)
DS2431X+
-40°C to +85°C 3x3 UCSPR (10k pcs)
Note: The leads of TO-92 packages on tape and reel are
formed to approximately 100-mil (2.54mm) spacing. For details,
refer to the package outline drawing.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*EP = Exposed pad.
19-4675; Rev 15; 3/15






DS2431 Datasheet, Funktion
DS2431
1024-Bit, 1-Wire EEPROM
DS2431 COMMAND LEVEL:
1-Wire ROM FUNCTION COMMANDS
(SEE FIGURE 9)
AVAILABLE COMMANDS: DATA FIELD AFFECTED:
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
RESUME
OVERDRIVE-SKIP ROM
OVERDRIVE-MATCH ROM
64-BIT REG. #, RC-FLAG
64-BIT REG. #, RC-FLAG
64-BIT REG. #, RC-FLAG
RC-FLAG
RC-FLAG
RC-FLAG, OD-FLAG
64-BIT REG. #, RC-FLAG, OD-FLAG
DS2431-SPECIFIC
MEMORY FUNCTION COMMANDS
(SEE FIGURE 7)
WRITE SCRATCHPAD
READ SCRATCHPAD
COPY SCRATCHPAD
READ MEMORY
64-BIT SCRATCHPAD, FLAGS
64-BIT SCRATCHPAD
DATA MEMORY, REGISTER PAGE
DATA MEMORY, REGISTER PAGE
Figure 2. Hierarchical Structure for 1-Wire Protocol
MSB
8-BIT
CRC CODE
MSB LSB MSB
Figure 3. 64-Bit Lasered ROM
48-BIT SERIAL NUMBER
LSB
8-BIT FAMILY CODE
(2Dh)
LSB MSB
LSB
The hierarchical structure of the 1-Wire protocol is shown
in Figure 2. The bus master must first provide one of
the seven ROM function commands: Read ROM, Match
ROM, Search ROM, Skip ROM, Resume, Overdrive-Skip
ROM, or Overdrive-Match ROM. Upon completion of an
Overdrive-Skip ROM or Overdrive-Match ROM command
byte executed at standard speed, the device enters over-
drive mode where all subsequent communication occurs
at a higher speed. The protocol required for these ROM
function commands is described in Figure 9. After a ROM
function command is successfully executed, the memory
functions become accessible and the master can provide
any one of the four memory function commands. The pro-
tocol for these memory function commands is described
in Figure 7. All data is read and written least signifi-
cant bit first.
64-Bit Lasered ROM
Each DS2431 contains a unique ROM code that is 64 bits
long. The first 8 bits are a 1-Wire family code. The next 48
bits are a unique serial number. The last 8 bits are a cyclic
redundancy check (CRC) of the first 56 bits. See Figure 3
for details. The 1-Wire CRC is generated using a polyno-
mial generator consisting of a shift register and XOR gates
as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1.
Additional information about the 1-Wire CRC is available
in Application Note 27: Understanding and Using Cyclic
Redundancy Checks with Maxim iButton® Products.
The shift register bits are initialized to 0. Then, starting
with the least significant bit of the family code, one bit at
a time is shifted in. After the 8th bit of the family code has
been entered, the serial number is entered. After the last
bit of the serial number has been entered, the shift reg-
ister contains the CRC value. Shifting in the 8 bits of the
CRC returns the shift register to all 0s.
iButton is a registered trademark of Maxim Integrated Products, Inc.
www.maximintegrated.com
Maxim Integrated 6

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DS2431 pdf, datenblatt
DS2431
1024-Bit, 1-Wire EEPROM
Read Scratchpad [AAh]
The Read Scratchpad command allows verifying the tar-
get address and the integrity of the scratchpad data. After
issuing the command code, the master begins reading.
The first two bytes are the target address. The next byte
is the ending offset/data status byte (E/S) followed by the
scratchpad data, which may be different from what the
master originally sent. This is of particular importance if
the target address is within the register page or a page
in either write-protection mode or EPROM mode. See the
Write Scratchpad [0Fh] section for details. The master
should read through the scratchpad (E[2:0] - T[2:0] + 1
bytes), after which it receives the inverted CRC based on
data as it was sent by the DS2431. If the master continues
reading after the CRC, all data is logic 1.
Copy Scratchpad [55h]
The Copy Scratchpad command is used to copy data
from the scratchpad to writable memory sections. After
issuing the Copy Scratchpad command, the master must
provide a 3-byte authorization pattern, which should
have been obtained by an immediately preceding Read
Scratchpad command. This 3-byte pattern must exactly
match the data contained in the three address registers
(TA1, TA2, E/S, in that order). If the pattern matches, the
target address is valid, the PF flag is not set, and the tar-
get memory is not copy protected, then the AA flag is set
and the copy begins. All 8 bytes of scratchpad contents
are copied to the target memory location. The duration
of the device’s internal data transfer is tPROG during
which the voltage on the 1-Wire bus must not fall below
2.8V. A pattern of alternating 0s and 1s are transmitted
after the data has been copied until the master issues a
reset pulse. If the PF flag is set or the target memory is
copy protected, the copy does not begin and the AA flag
is not set.
Read Memory [F0h]
The Read Memory command is the general function to
read data from the DS2431. After issuing the command,
the master must provide the 2-byte target address. After
these 2 bytes, the master reads data beginning from the
target address and can continue until address 008Fh. If
the master continues reading, the result is logic 1s. The
device’s internal TA1, TA2, E/S, and scratchpad contents
are not affected by a Read Memory command.
1-Wire Bus System
The 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances the DS2431 is
a slave device. The bus master is typically a microcon-
troller. The discussion of this bus system is broken down
into three topics: hardware configuration, transaction
sequence, and 1-Wire signaling (signal types and timing).
The 1-Wire protocol defines bus transactions in terms of
the bus state during specific time slots, which are initiated
on the falling edge of sync pulses from the bus master.
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device
attached to the 1-Wire bus must have open-drain or three-
state outputs. The 1-Wire port of the DS2431 is open drain
with an internal circuit equivalent to that shown in Figure 8.
A multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS2431 supports both a standard
and overdrive communication speed of 15.4kbps (max)
and 125kbps (max), respectively. Note that legacy 1-Wire
products support a standard communication speed of
16.3kbps and overdrive of 142kbps. The slightly reduced
rates for the DS2431 are a result of additional recovery
times, which in turn were driven by a 1-Wire physical
interface enhancement to improve noise immunity. The
value of the pullup resistor primarily depends on the net-
work size and load conditions. The DS2431 requires a
pullup resistor of 2.2kΩ (max) at any speed.
The idle state for the 1-Wire bus is high. If for any reason
a transaction needs to be suspended, the bus must be
left in the idle state if the transaction is to resume. If this
does not occur and the bus is left low for more than 16μs
(overdrive speed) or more than 120μs (standard speed),
one or more devices on the bus could be reset.
Transaction Sequence
The protocol for accessing the DS2431 through the
1-Wire port is as follows:
● Initialization
● ROM Function Command
● Memory Function Command
● Transaction/Data
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Maxim Integrated 12

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