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PDF STGIB15CH60TS-E Data sheet ( Hoja de datos )
| Número de pieza | STGIB15CH60TS-E | |
| Descripción | 3-phase inverter / short-circuit rugged IGBTs | |
| Fabricantes | STMicroelectronics | |
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STGIB15CH60TS-E
SLLIMM™ - 2nd series
IPM, 3-phase inverter, 20 A, 600 V short-circuit rugged IGBTs
Datasheet - production data
Applications
• 3-phase inverters for motor drives
• Home appliances such as washing machines,
refrigerators, air conditioners and sewing
machines
Features
• IPM 20 A, 600 V 3-phase IGBT inverter bridge
including 2 control ICs for gate driving and
freewheeling diodes
• 3.3 V, 5 V TTL/CMOS inputs with hysteresis
• Internal bootstrap diode
• Undervoltage lockout of gate drivers
• Smart shutdown function
• Short-circuit protection
• Shutdown input/fault output
• Separate open emitter outputs
• Built-in temperature sensor
• Comparator for fault protection
• Short-circuit rugged TFS IGBTs
• Very fast, soft recovery diodes
• 85 kΩ NTC UL 1434 CA 4 recognized
• Fully isolated package
• Isolation rating of 1500 Vrms/min
Description
This second series of SLLIMM (small low-loss
intelligent molded module) provides a compact,
high performance AC motor drive in a simple,
rugged design. It combines new ST proprietary
control ICs (one LS and one HS driver) with an
improved short-circuit rugged trench gate field-
stop (TFS) IGBT, making it ideal for 3-phase
inverter systems such as home appliances and air
conditioners. SLLIMM™ is a trademark of
STMicroelectronics.
Order code
STGIB15CH60TS-E
Table 1. Device summary
Marking
Package
GIB15CH60TS-E
SDIP2B-26L
Packaging
Tube
September 2015
This is information on a product in full production.
DocID026590 Rev 4
1/25
www.st.com
1 page  
STGIB15CH60TS-E
2 Absolute maximum ratings
Absolute maximum ratings
(Tj= 25°C unless otherwise noted).
Symbol
Table 3. Inverter parts
Parameter
VPN Supply voltage between P -NU, -NV, -NW
VPN(surge) Supply voltage surge between P -NU, -NV, -NW
VCES Collector-emitter voltage each IGBT
Continuous collector current each IGBT (TC = 25 °C)
±IC
Continuous collector current each IGBT (TC = 80 °C)
±ICP Peak collector current each IGBT (less than 1ms)
PTOT Total dissipation at TC=25°C each IGBT
tscw
Short circuit withstand time, VCE = 300V, TJ = 125 °C,
VCC = Vboot = 15 V, VIN = 0 to 5 V
Value
450
500
600
20
15
40
81
5
Unit
V
V
V
A
A
W
µs
Symbol
VCC
VBOOT
VOUT
VCIN
VIN
VSD/OD
ISD/OD
VTSO
ITSO
Table 4. Control parts
Parameter
Supply voltage between VCCH-GND, VCCL-GND
Bootstrap voltage
Output voltage between U, V, W and GND
Comparator input voltage
Logic input voltage applied between HINx, LINx and
GND
Open drain voltage
Open drain sink current
Temperature sensor output voltage
Temperature sensor output current
Min
-0.3
-0.3
VBOOT -
21
-0.3
-0.3
-0.3
-
-0.3
Max
20
619
VBOOT +
0.3
20
15
7
10
5.5
7
Unit
V
V
V
V
V
V
mA
V
A
Table 5. Total system
Symbol
Parameter
VISO
Isolation withstand voltage applied between each pin and
heat sink plate (AC voltage, t = 60sec.)
TJ Power chips operating junction temperature
TC Module case operation temperature
Value
1500
-40 to 175
-40 to 125
Unit
Vrms
°C
°C
DocID026590 Rev 4
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STGIB15CH60TS-E
4 Fault management
Fault management
The device integrates an open-drain output connected to SD Pin. As soon as a fault occurs,
the open-drain is activated and LVGx outputs are forced low. Two types of fault can be
detected:
• Overcurrent (OC) sensed by the internal comparator (see more detail in Section 4.2:
Smart shutdown function);
• Undervoltage on supply voltage (VCC);
Each fault enables the SD open drain for a different time; refer to the following Table 10:
Fault timing.
Table 10. Fault timing
Symbol
Parameter
Event time
SD open-drain enable
time result
OC Overcurrent event
≤ 20 μs
≥ 20 µs
20 μs
OC time
≤ 50 μs
50 µs
UVLO
Undervoltage lock out event
≥ 50µs
until the VCC_LS exceed the
VCC_LS UV turn ON threshold
UVLO time
The device actually remains in a fault condition (SD at low logic level and LVGx outputs
disabled) for a time that also depends on the RC network connected to the SD pin. The
network generates a time interval that is added to the internal value.
Figure 4. Overcurrent timing (without contribution of RC network on SD)
DocID026590 Rev 4
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