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PDF ADP2504 Data sheet ( Hoja de datos )
| Número de pieza | ADP2504 | |
| Descripción | DC-to-DC Converters | |
| Fabricantes | Analog Devices | |
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Data Sheet
600 mA/1000 mA, 2.5 MHz Buck-Boost
DC-to-DC Converters
ADP2503/ADP2504
FEATURES
GENERAL DESCRIPTION
1 mm height profile
Compact PCB footprint
Seamless transition between modes
38 μA typical quiescent current
2.5 MHz operation enables 1.5 μH inductor
Input voltage: 2.3 V to 5.5 V
Fixed output voltage: 2.8 V to 5.0 V
Adjustable model output voltage range: 2.8 V to 5.5 V
600 mA (ADP2503) and 1000 mA (ADP2504) output options
Boost converter configuration with load disconnect
SYNC pin with three different modes
Power save mode (PSM) for improved light load efficiency
Forced fixed frequency operation mode
Synchronization with external clock
Internal compensation
Soft start
Enable/shutdown logic input
Overtemperature protection
Short-circuit protection
Undervoltage lockout protection
Small 10-lead 3 mm × 3 mm LFCSP (QFN) package
Supported by ADIsimPower™ design tool
APPLICATIONS
Wireless handsets
Digital cameras/portable audio players
Miniature hard disk power supplies
USB powered devices
The ADP2503/ADP2504 are high efficiency, low quiescent current
step-up/step-down dc-to-dc converters that can operate at input
voltages greater than, less than, or equal to the regulated output
voltage. The power switches and synchronous rectifiers are
internal to minimize external device count. At high load currents,
the ADP2503/ADP2504 use a current-mode, fixed frequency
pulse-width modulation (PWM) control scheme for optimal
stability and transient response. To ensure the longest battery life
in portable applications, the ADP2503/ADP2504 have an optional
power save mode that reduces the switching frequency under
light load conditions. For wireless and other low noise applica-
tions where variable frequency power save mode may cause
interference, the logic control input sync forces fixed frequency
PWM operation under all load conditions.
The ADP2503/ADP2504 can run from input voltages between
2.3 V and 5.5 V, allowing single lithium or lithium polymer cell,
multiple alkaline or NiMH cells, PCMCIA, USB, and other stan-
dard power sources. The ADP2503/ADP2504 have fixed output
options, or using the adjustable model, the output voltage can
be programmed through an external resistor divider. Compensa-
tion is internal to minimize the number of external components.
During logic-controlled shutdown, the input is disconnected
from the output and draws less than 1 μA from the input source.
Operating as boost converters, the ADP2503/ADP2504 feature a
true load disconnect function that isolates the load from the
power source. Other key features include undervoltage lockout
to prevent deep battery discharge, and soft start to prevent input
current overshoot at startup.
TYPICAL APPLICATION CIRCUIT
1.5µH
VIN
2.3V TO 5.5V
10µF
SW1
SW2
ADP2503/ADP2504
PVIN
VOUT
VIN FB
VOUT
2.8V TO 5V
22µF
SYNC1
EN AGND PGND
ON
OFF
1ALLOWS THE ADP2503/ADP2504 TO OPERATE IN
THREE DIFFERENT MODES.
Figure 1.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADP2503/ADP2504
VOUT 1
SW2 2
PGND 3
SW1 4
PVIN 5
ADP2503/
ADP2504
TOP VIEW
(Not to scale)
10 FB
9 AGND
8 VIN
7 SYNC
6 EN
NOTES
1. CONNECT THE EXPOSED PAD TO PGND.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
VOUT
Output of the ADP2503/ADP2504. Connect the output capacitor between VOUT and PGND.
2 SW2 Power Switch 2 Connection. This is the internal connection to the input PMOS and NMOS switches. Connect
SW2 to the inductor with a short, wide track.
3
PGND
Power GND. Connect the input and output capacitors and the PGND pin to a PGND plane.
4 SW1 Power Switch 1 Connection. This is the internal connection to the output PMOS and NMOS switches. Connect
SW1 to the inductor with a short, wide track.
5 PVIN Power Input. This the input to the buck-boost power switches. Place a 10 μF capacitor between PVIN and
PGND as close as possible to the ADP2503/ADP2504.
6 EN
Enable. Drive EN high to turn on the ADP2503/ADP2504. Bring EN low to put the device into shutdown mode.
7
SYNC
The SYNC pin permits the ADP2503/ADP2504 to operate in three different modes.
Normal operation: with SYNC driven low, the ADP2503/ADP2504 operate at 2.5 MHz PWM mode for heavy
and medium loads, and moves to power save mode (PSM) mode for light loads.
Forced PWM operation: with SYNC driven high, the ADP2503/ADP2504 operate at fixed 2.5 MHz PWM mode
for all load conditions.
SYNC mode: to synchronize the ADP2503/ADP2504 switching to an external signal, drive this pin with a clock
between 2.2 MHz and 2.8 MHz. The SYNC signal must have on and off times greater than 160 ns.
8 VIN
Analog Power Supply. This is the supply for the ADP2503/ADP2504 internal circuitry.
9
AGND
Analog Ground.
10 FB
Output Feedback. This is an input to the internal error amplifier and must be connected to VOUT on fixed
output versions; for the adjustable model, this is the voltage feedback.
EP Exposed pad Connect the exposed pad to PGND.
Rev. D | Page 5 of 16
5 Page 
Data Sheet
ADP2503/ADP2504
THEORY OF OPERATION
VIN
8
ADP2503/ADP2504
BIASING
SW1
4
1.5µH
SW2
2
ADP2503/ADP2504
VBAT = 2.3V
TO 5.5V
10µF
PVIN
5
2.25V
PMOS1
NMOS1
UVLO
NMOS2
BAND GAP
REFERENCE
EN EN
6
THERMAL
PROTECTION
PWM CONTROL
PMOS2
VOUT
1
SOFT START
FB
10
–0.5V
CS
SYNC
7
PGND
3
AGND
9
OSCILLATOR
Figure 29. ADP2503/ADP2504 Block Diagram
22µF
The ADP2503/ADP2504 are synchronous average current-mode
switching buck-boost regulators designed to maintain a fixed
output voltage VOUT from an input supply VIN that can be
greater than, equal to, or less than VOUT. When VIN is signifi-
cantly greater than VOUT, the device is in buck mode: PMOS2 is
always active, NMOS2 is always off, and the PMOS1 and NMOS1
switches constitute a buck converter. When VIN is significantly
lower than VOUT, the device is in boost mode: PMOS1 is always
active, NMOS1 is always off, and the NMOS2 and PMOS2
switches constitute a boost converter. When VIN is in the range
[VOUT ± 10%], the ADP2503/ADP2504 automatically enter the
buck-boost mode. In buck-boost mode, the two operations,
buck (PMOS1 and NMOS1 switching in antiphase) and boost
(NMOS2 and PMOS2 switching in antiphase), take place at each
period of the clock. This is aimed at maintaining the regulation
and keeping a minimal current ripple in the inductor to guaran-
tee good transient performances.
POWER SAVE MODE
When the SYNC pin is low, the ADP2503/ADP2504 can operate
in power save mode (PSM). In this mode, when the load current
becomes less than 75 mA nominally at VIN = 3.6 V, the control-
ler pulls up VOUT and then halts the switching regime until VOUT
goes back to a restart value. Then VOUT is pulled up again for a
new cycle. This minimizes the switching losses at light load. When
the load rises above 150 mA, the ADP2503/ADP2504 revert to
fixed PWM mode. This results in about 75 mA of hysteresis
between PSM and fixed PWM, preventing oscillations between
these two modes.
SOFT START
When the ADP2503/ADP2504 are started, VOUT is ramped from
0 V to its final programmed value in 200 μs (typical). This limits
the inrush current to less than 600 mA for a nominal output
capacitor of 20 μF. Because the VOUT start-up slope is constant,
the inrush current becomes larger if the output capacitor is
made larger.
SYNC FUNCTION
When the SYNC pin is high, PSM is deactivated. The ADP2503/
ADP2504 always operate in PWM using the internal oscillator.
When the SYNC pin is switching in the 2.1 MHz to 2.9 MHz
range, the regulator switching frequency slides to the frequency
applied on SYNC and then locks on it. When the SYNC pin
stops switching, the regulator switching frequency slides back to
the internal oscillator frequency.
ENABLE
The device starts operation with soft start when the EN pin
is brought high. Pulling the EN pin low forces the device into
shutdown, with a typical shutdown current of 0.2 μA.
In this mode, the PMOS power switches are turned off, the
NMOS power switches are turned on, and the control circuitry
is not enabled. For proper operation, the EN pin must be
terminated and must not be left floating.
Rev. D | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADP2504.PDF ] | |
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