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GM8128 Schematic ( PDF Datasheet ) - Grain Media

Teilenummer GM8128
Beschreibung H.264 IP CAM SoC
Hersteller Grain Media
Logo Grain Media Logo 




Gesamt 30 Seiten
GM8128 Datasheet, Funktion
GM8125/GM8126/GM8128
H.264 IP CAM SOC
Data Sheet
Rev.: 0.4
Issue Date: June 2011






GM8128 Datasheet, Funktion
Chapter 2
Chapter 3
Chapter 4
Chapter 5
1.3.25 UART Controller .......................................................................................... 22
1.3.26 Secure Digital Card (SDC) Controller ......................................................... 22
1.3.27 Comparsion Table of GM8125/GM8126/GM8128....................................... 23
1.3.28 Comparsion Table of E-PAD TQFP-176 and TFBGA-256 .......................... 23
Signal Description ............................................................................................................... 25
2.1 Signal Description .................................................................................................... 26
2.2 TFBGA-256 Pin Assignments .................................................................................. 36
Memory Map ....................................................................................................................... 37
3.1 Memory Map ............................................................................................................ 38
Power Management Unit..................................................................................................... 39
4.1 General Description.................................................................................................. 40
4.2 Features ................................................................................................................... 40
4.3 Clock Manager ......................................................................................................... 41
4.3.1 32.768-kHz Oscillator .................................................................................. 42
4.3.2 Core PLL (PLL1).......................................................................................... 42
4.3.3 Peripheral PLL (PLL2)................................................................................. 43
4.3.4 Clock Gating................................................................................................ 43
4.3.5 Hardware Reset .......................................................................................... 44
4.3.6 Watchdog Reset .......................................................................................... 44
4.3.7 Normal Mode............................................................................................... 44
4.3.8 IDLE Mode .................................................................................................. 45
4.3.9 Standby Mode ............................................................................................. 45
4.3.10 Sleep Mode ................................................................................................. 46
4.3.11 Frequency Change Sequence (FCS).......................................................... 46
4.4 Programming Model ................................................................................................. 48
4.4.1 Summary of Clock and Power Manager Registers ..................................... 48
4.4.2 Register Descriptions .................................................................................. 49
FA626TE ........................................................................................................................... 107
5.1 General Description................................................................................................ 108
5.2 Block Diagram ........................................................................................................ 109
5.2.1 CPU Core .................................................................................................. 109
5.2.2 Branch Prediction Unit (BPU).................................................................... 110
5.2.3 Instruction Cache (ICache) ....................................................................... 110
5.2.4 Data Cache (DCache) ............................................................................... 110
GM8125/GM8126/GM8128 Data Sheet
www.grain-media.com
ii

6 Page









GM8128 pdf, datenblatt
Chapter 16
15.5.1 Summary of Control Registers .................................................................. 335
15.5.2 LCD Global Parameters ............................................................................ 337
15.5.3 LCD Timing and Polarity Parameters........................................................ 345
15.5.4 LCD Output Format Parameters ............................................................... 348
15.5.5 Scaler Control Registers ........................................................................... 353
15.5.6 Virtual Screen............................................................................................ 357
15.5.7 OSD Control Registers for Simple OSD.................................................... 358
15.5.8 OSD Font Database Write Accessing Port (Offset 0x8000 ~ 0xBFFC) .... 361
15.5.9 OSD Window Attribute Write Accessing Port (Offset 0xC000 ~ 0xC7FC) 361
10/100 Ethernet Controller ................................................................................................ 363
16.1 General Description................................................................................................ 364
16.2 Features ................................................................................................................. 364
16.3 Interface Clocking................................................................................................... 365
16.4 Register Definition .................................................................................................. 365
16.4.1 Interrupt Status Register, ISR, 32’h0 (Offset: 0x00 ~ 0x03) ...................... 365
16.4.2 Interrupt Enable Register, IME, 32’h0 (Offset: 0x04 ~ 0x07) .................... 366
16.4.3 MAC Most Significant Address Register, MAC_MADR, 32’h0 (Offset: 0x08 ~
0x0B) ................................................................................................................... 366
16.4.4 MAC Least Significant Address Register, MAC_LADR, 32’h0 (Offset: 0x0C ~
0x0F) ................................................................................................................... 366
16.4.5 Multicast Address Hash Table 0 Register, MAHT0, 32’h0 (Offset: 0x10 ~
0x13) ................................................................................................................... 367
16.5 Multicast Address Hash Table 1 Register, MAHT1, 32’h0 (Offset: 0x14 ~ 0x17).. 367
16.5.1 Transmit Poll Demand Register, TXPD, 32’h0 (Offset: 0x18 ~ 0x1B)....... 367
16.5.2 Receive Poll Demand Register, RXPD, 32’h0 (Offset: 0x1C ~ 0x1F)....... 367
16.5.3 Transmit Ring Base Address Register, TXR_BADR, 32’h0 (Offset: 0x20 ~
0x23) ................................................................................................................... 368
16.5.4 Receive Ring Base Address Register, RXR_BADR, 32’h0 (Offset: 0x24 ~
0x27) ................................................................................................................... 368
16.5.5 Interrupt Timer Control Register, ITC, 32’h0 (Offset: 0x28 ~ 0x2B) .......... 368
16.5.6 Automatic Polling Timer Control Register, APTC, 32’h0, (Offset: 0x2C ~ 0x2F)
................................................................................................................... 371
16.5.7 DMA Burst Length and Arbitration Control Register, DBLAC, 32’h0, (Offset:
0x30 ~ 0x33) ......................................................................................................... 373
16.5.8 Revision Register, REVR, 32’h0, (Offset: 0x34 ~ 0x37)............................ 375
16.5.9 Feature Register, FEAR, 32’h0, (Offset: 0x38 ~ 0x3B) ............................. 375
GM8125/GM8126/GM8128 Data Sheet
www.grain-media.com
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12 Page





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