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83C152JB Schematic ( Datenblatt PDF ) - Intel

Teilenummer 83C152JB
Beschreibung Universal Communication Controller 8-Bit Microcontroller
Hersteller Intel
Logo Intel Logo 

Gesamt 17 Seiten
		
83C152JB Datasheet, Funktion
8XC152JA JB JC JD
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCONTROLLER
X 8K Factory Mask Programmable ROM Available
Y Superset of 80C51 Architecture
Y Multi-Protocol Serial Communication
I O Port (2 048 Mbps 2 4 Mbps Max)
SDLC HDLC Only
CSMA CD and SDLC HDLC
User Definable Protocols
Y Full Duplex Half Duplex
Y MCS -51 Compatible UART
Y 16 5 MHz Maximum Clock Frequency
Y Multiple Power Conservation Modes
Y 64KB Program Memory Addressing
Y 64KB Data Memory Addressing
Y 256 Bytes On-Chip RAM
Y Dual On-Chip DMA Channels
Y Hold Hold Acknowledge
Y Two General Purpose Timer Counters
Y 5 or 7 I O Ports
Y 56 Special Function Registers
Y 11 Interrupt Sources
Y Available in 48 Pin Dual-in-Line Package
and 68 Pin Surface Mount PLCC
Package
(See Packaging Spec Order 231369)
The 80C152 which is based on the MCS -51 CPU is a highly integrated single-chip 8-bit microcontroller
designed for cost-sensitive high-speed serial communications It is well suited for implementing Integrated
Services Digital Networks (ISDN) emerging Local Area Networks and user defined serial backplane applica-
tions In addition to the multi-protocol communication capability the 80C152 offers traditional microcontroller
features for peripheral I O interface and control
Silicon implementations are much more cost effective than multi-wire cables found in board level parallel-to-
serial and serial-to-parallel converters The 83C152 contains in silicon all the features needed for the serial-
to-parallel conversion Other 83C152 benefits include 1) better noise immunity through differential signaling or
fiber optic connections 2) data integrity utilizing the standard designed in CRC checks and 3) better modulari-
ty of hardware and software designs All of these cost network parameter and real estate improvements
apply to 83C152 serial links between boards or systems and 83C152 serial links on a single board
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
October 1989
Order Number 270431-003






83C152JB Datasheet, Funktion
8XC152JA JB JC JD
Pin
47-40 65-58
9 13
38 55
37 54
39 56
23 32
22 31
N A 17 20
21 22
38 39
40 49
N A 67 66
52 57
50 68
1 51
N A 12
N A 53
Pin Description (Continued)
Pin Description
Port 4 Port 4 is an 8-bit bidirectional I O port with internal pullups Port 4 pins that
have 1s written to them are pulled high by the internal pullups and in that state can
be used as inputs As inputs Port 4 pins that are externally being pulled low will
source current (IIL on the data sheet) because of the internal pullups In addition
Port 4 also receives the low-order address bytes during program verification
RST Reset input A logic low on this pin for three machine cycles while the
oscillator is running resets the device An internal pullup resistor permits a power-on
reset to be generated using only an external capacitor to VSS Although the GSC
recognizes the reset after three machine cycles data may continue to be
transmitted for up to 4 machine cycles after Reset is first applied
ALE Address Latch Enable output signal for latching the low byte of the address
during accesses to external memory
In normal operation ALE is emitted at a constant rate of the oscillator
frequency and may be used for external timing or clocking purposes Note
however that one ALE pulse is skipped during each access to external Data
Memory While in Reset ALE remains at a constant high level
PSEN Program Store Enable is the Read strobe to External Program Memory
When the 8XC152 is executing from external program memory PSEN is active
(low) When the device is executing code from External Program Memory PSEN is
activated twice each machine cycle except that two PSEN activations are skipped
during each access to External Data Memory While in Reset PSEN remains at a
constant high level
EA External Access enable EA must be externally pulled low in order to enable
the 8XC152 to fetch code from External Program Memory locations 0000H to
0FFFH
EA must be connected to VCC for internal program execution
XTAL1 Input to the inverting oscillator amplifier and input to the internal clock
generating circuits
XTAL2 Output from the inverting oscillator amplifier
Port 5 Port 5 is an 8-bit bidirectional I O port with internal pullups Port 5 pins that
have 1s written to them are pulled high by the internal pullups and in that state can
be used as inputs As inputs Port 5 pins that are externally being pulled low will
source current (IIL on the data sheet) because of the internal pullups
Port 5 is also the multiplexed low-order address and data bus during accesses to
external program memory if EBEN is pulled high In this application it uses strong
pullups when emitting 1s
Port 6 Port 6 is an 8-bit bidirectional I O port with internal pullups Port 6 pins that
have 1s written to them are pulled high by the internal pullups and in that state can
be used as inputs As inputs Port 6 pins that are externally pulled low will source
current (IIL on the data sheet) because of the internal pullups
Port 6 emits the high-order address byte during fetches from external Program
Memory if EBEN is pulled high In this application it uses strong pullups when
emitting 1s
EBEN E-Bus Enable input that designates whether program memory fetches take
place via Ports 0 and 2 or Ports 5 and 6 Table 1 shows how the ports are used in
conjunction with EBEN
EPSEN E-bus Program Store Enable is the Read strobe to external program
memory when EBEN is high Table 2 shows when EPSEN is used relative to PSEN
depending on the status of EBEN and EA
6

6 Page







83C152JB pdf, datenblatt
8XC152JA JB JC JD
EXTERNAL DATA MEMORY WRITE CYCLE
270431 – 10
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min Max Units
1 TCLCL
Oscillator Frequency
35
16 5
MHz
TCHCX
High Time
20
ns
TCLCX
Low Time
20
ns
TCLCH
Rise Time
20 ns
TCHCL
Fall Time
20 ns
EXTERNAL CLOCK DRIVE WAVEFORM
270431 – 11
12

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