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WM8144-12 Schematic ( PDF Datasheet ) - Wolfson Microelectronics

Teilenummer WM8144-12
Beschreibung Integrated 12-bit Data Acquisition System
Hersteller Wolfson Microelectronics
Logo Wolfson Microelectronics Logo 




Gesamt 27 Seiten
WM8144-12 Datasheet, Funktion
WM8144-12
Production Data
February 1998 Rev. 4.1
Integrated 12-bit Data Acquisition System for
Imaging Applications
Description
Features
WM8144-12 integrates the analogue signal conditioning
required by CCD sensors with a 12-bit ADC and optional
pixel-by-pixel image compensation. WM8144-12 requires
minimal external circuitry and provides a cost effective
sensor-to-digital domain system solution.
Each analogue conditioning channel provides reset level
clamp, CDS, fine offset level shifting and gain
amplification. The three channels are multiplexed into the
ADC. Output from the ADC can either be direct or passed
through a digital post-processing function. The post-
processing provides compensation for variations in offset
and shading on a pixel-by-pixel basis.
• Reset level clamp
• Correlated Double Sampling (CDS)
• Fine offset level shifting
• Programmable Gain Amplification
• 12-Bit ADC with maximum 4 MSPS
• Digital post-processing for pixel-by-pixel
image compensation
• Simple clocking scheme
• Control by serial or parallel interface
• Time-multiplexed eight-bit data output mode
• 48 pin TQFP package
• Pin compatible with WM8144-10
The flexible output architecture allows twelve-bit data to
be accessed either on a twelve-bit bus or via a time-
multiplexed eight-bit bus. The WM8144-12 can be
configured for pixel-by-pixel or line-by-line multiplexing
operation. Reset level clamp and/or CDS features can be
optionally bypassed. Device configuration is either by a
simple serial or eight-bit parallel interface.
Applications
• Document scanners
• CCD sensor interfaces
• Contact image sensor (CIS) interfaces
Block Diagram
VRLC
VRU VRT
VRB VRL
VMID
VSMP MCLK RLC
AVDD AGND DVDD1 DVDD2 DGND
VMID
RINP
GINP
BINP
MUX
CL RS VS
S/H
S/H
PGA
CDS
5-BIT REG
S/H
S/H
PGA
CDS
5-BIT REG
S/H
S/H
PGA
CDS
5-BIT REG
TIMING CONTROL
OFFSET
8-BIT + SIGN
DAC
VMID
OFFSET
8-BIT + SIGN
DAC
VMID
OFFSET
8-BIT + SIGN
DAC
VMID
WM8144-12
EXTERNAL
DATA STORE
INTERFACE
M
U
X
12 BIT
ADC
IMAGE
COMPENSATION
PROCESSING
12/8
MUX
CONFIGURABLE
SERIAL/PARALLEL
CONTROL INTERFACE
CC[2:0]
DV
CDATA(7:0)
ORNG
OEB
OP[11:0]
PNS
SDI / DNA
SCK / RNW
SEN / STB
NRESET
Production Data data sheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics standard terms and condi-
tions.
Wolfson Microelectronics
Lutton Court, Bernard Terrace, Edinburgh EH8 9NX, UK
Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176
www: http://www.wolfson.co.uk
© 1998 Wolfson Microelectronics
1






WM8144-12 Datasheet, Funktion
WM8144-12
Pin Descriptions
Pin No.
23
22
21
33
34
35
36
37
38
39
40
32
31
29
19
13
14
15
16
20
42
43
44
45
46
47
48
1
2
3
5
6
Name
RINP
GINP
BINP
CDATA[7]
CDATA[6]
CDATA[5]
CDATA[4]
CDATA[3]
CDATA[2]
CDATA[1]
CDATA[0]
MCLK
VSMP
RLC
VRLC
VRT
VRB
VRU
VRL
VMID
OP[11]
OP[10]
OP[9]
OP[8]
OP[7]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[0]
Type
Analogue IP
Analogue IP
Analogue IP
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IP
Digital IP
Digital IP
Analogue OP
Analogue IP
Analogue IP
Analogue IP
Analogue IP
Analogue OP
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Description
Red Channel input video
Green Channel input video
Blue Channel input video
Image compensation data read/write at twice ADC conversion rate
Master clock. This clock is applied at either six, four or two times the input
pixel rate depending on the operational mode. MCLK is divided internally
to define the ADC samples rate and to provide the clock source for digital
logic.
Video sample synchronisation pulse. This signal is applied synchronously
with MLCK to specify the point in time that the input is sampled. The timing
of internal multiplexing between the R, G and B channels is derived from
this signal
Selects whether reset level clamp is applied on a pixel-by-pixel basis. If
RLC is required on each pixel then this pin can be tied high
Selectable analogue output voltage for RLC
ADC reference voltages. The ADC reference range is applied between
VRT (full scale) and VRB (zero level). VRU and VRL can be used to
derive optimum reference voltages from an external 5V reference
Buffered mid-point of ADC reference string.
Tri-state digital 10-bit bi-directional bus. There are four modes:
Tri-state:
when OEB = 1
Output twelve-bit:
twelve bit data is output from bus
Output 8-bit multiplexed: data output on OP[11:4] at 2 * ADC conversion
rate
Input 8-bit:
control data is input on bits OP[11:4]
Wolfson Microelectronics
6

6 Page









WM8144-12 pdf, datenblatt
WM8144-12
Theory of Operation (Contd)
Example of Gain and Offset Operation
Input Video polarity
negative
Input sampling
CDS
Input voltage amplitude (VVS - VRS) 1.6V
Programmable gain
x1
Clamping
Yes, VCL = 3.5V
After the input capacitor the input to the WM8144-12 can
be represented as:
Vrs
RS VS
Vvs
Figure 7
For a black pixel:
VRS = VCL
VVS = VCL
Assuming that the offset DAC is set to 00dec:
VADC
=
1*
(Vcl
-
Vcl)
+
(1
2
*
0)
*
0
255
VMID
*
VMID
2 
+
VMID
VADC = 0 + 0 + VMID
VADC = VMID
An input voltage of VMID corresponds to a code of
2048(dec) from the ADC.
To maximise the dynamic range of the ADC input it is
necessary to program the offset DAC code to move the
ADC code corresponding to the black level towards code
4096(dec).
Hence set the offset DAC to 164(dec) with the sign bit
not set.
164 VMID
VADC = 1*(VCL - VCL) + (1 - 2*0) *
*
+ VMID
255 2
82
VADC = 0 + 255 * VMID + VMID
337
VADC = 255 * VMID
When the VMID is 2.5v, the ADC input voltage becomes
3.3 volts which will result in an ADC code of 3686(dec).
This is near the ideal full-scale of 4095(dec).
For a white pixel:
VRS = VCL
VVS = VCL - 1.6
For the white pixel, using the same offset DAC value, the
ADC input can be expressed as:
164 VMID
VADC = 1*(VCL - 1.6 - VCL) + (1 - 2*0) *
*
+ VMID
255 2
82
VADC = -1.6 + 255 * VMID + VMID
337
VADC = 255 * VMID - 1.6
When the VMID is 2.5V, the ADC input voltage becomes
1.7 volts which will result in a code of 409(dec). This is
near the ideal full-scale of 000(dec).
Therefore the output codes from the ADC are between
3686(dec) and 409(dec), which implies that the ADC
input has been set up to maximise the dynamic range
available. If a digital representation of the ADC output
with a black level near 000(dec) and a white level near
4095(dec) is required then the INVOP control bit should
now be set to ONE.
Wolfson Microelectronics
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