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EPM3064A Schematic ( PDF Datasheet ) - Altera

Teilenummer EPM3064A
Beschreibung Programmable Logic Device Family
Hersteller Altera
Logo Altera Logo 




Gesamt 30 Seiten
EPM3064A Datasheet, Funktion
June 2003, ver. 3.4
®
MAX 3000A
Programmable Logic
Device Family
Data Sheet
Features...
High–performance, low–cost CMOS EEPROM–based programmable
logic devices (PLDs) built on a MAX® architecture (see Table 1)
3.3-V in-system programmability (ISP) through the built–in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
– ISP circuitry compliant with IEEE Std. 1532
Built–in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1-1990
Enhanced ISP features:
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in–system programming
High–density PLDs ranging from 600 to 10,000 usable gates
4.5–ns pin–to–pin logic delays with counter frequencies of up to
227.3 MHz
MultiVoltTM I/O interface enabling the device core to run at 3.3 V,
while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic
levels
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier
(PLCC), and FineLine BGATM packages
Hot–socketing support
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
Industrial temperature range
Table 1. MAX 3000A Device Features
Feature
Usable gates
Macrocells
Logic array blocks
Maximum user I/O
pins
tPD (ns)
tSU (ns)
tCO1 (ns)
fCNT (MHz)
EPM3032A
600
32
2
34
4.5
2.9
3.0
227.3
EPM3064A
1,250
64
4
66
4.5
2.8
3.1
222.2
Altera Corporation
DS-MAX3000A-3.4
EPM3128A
2,500
128
8
98
5.0
3.3
3.4
192.3
EPM3256A
5,000
256
16
161
7.5
5.2
4.8
126.6
EPM3512A
10,000
512
32
208
7.5
5.6
4.7
116.3
1






EPM3064A Datasheet, Funktion
MAX 3000A Programmable Logic Device Family Data Sheet
Macrocells
MAX 3000A macrocells can be individually configured for either
sequential or combinatorial logic operation. Macrocells consist of three
functional blocks: logic array, product–term select matrix, and
programmable register. Figure 2 shows a MAX 3000A macrocell.
Figure 2. MAX 3000A Macrocell
LAB Local Array
36 Signals
from PIA
16 Expander
Product Terms
Parallel Logic
Expanders
(from other
macrocells)
Global Global
Clear Clocks
2
Product-
Term
Select
Matrix
Clock/
Enable
Select
VCC
Clear
Select
Programmable
Register
Register
Bypass
PRN
D/T Q
ENA
CLRN
To I/O
Control
Block
Shared Logic
Expanders
To PIA
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product–term select matrix
allocates these product terms for use as either primary logic inputs (to the
OR and XOR gates) to implement combinatorial functions, or as secondary
inputs to the macrocell’s register preset, clock, and clock enable control
functions.
Two kinds of expander product terms (“expanders”) are available to
supplement macrocell logic resources:
Shareable expanders, which are inverted product terms that are fed
back into the logic array
Parallel expanders, which are product terms borrowed from adjacent
macrocells
The Altera development system automatically optimizes product–term
allocation according to the logic requirements of the design.
6 Altera Corporation

6 Page









EPM3064A pdf, datenblatt
MAX 3000A Programmable Logic Device Family Data Sheet
In–System
Programma-
bility
MAX 3000A devices can be programmed in–system via an industry–
standard four–pin IEEE Std. 1149.1-1990 (JTAG) interface. In-system
programmability (ISP) offers quick, efficient iterations during design
development and debugging cycles. The MAX 3000A architecture
internally generates the high programming voltages required to program
its EEPROM cells, allowing in–system programming with only a single
3.3–V power supply. During in–system programming, the I/O pins are
tri–stated and weakly pulled–up to eliminate board conflicts. The pull–up
value is nominally 50 k.
MAX 3000A devices have an enhanced ISP algorithm for faster
programming. These devices also offer an ISP_Done bit that ensures safe
operation when in–system programming is interrupted. This ISP_Done
bit, which is the last bit programmed, prevents all I/O pins from driving
until the bit is programmed.
ISP simplifies the manufacturing flow by allowing devices to be mounted
on a printed circuit board (PCB) with standard pick–and–place equipment
before they are programmed. MAX 3000A devices can be programmed by
downloading the information via in–circuit testers, embedded processors,
the MasterBlaster communications cable, the ByteBlasterMV parallel port
download cable, and the BitBlaster serial download cable. Programming
the devices after they are placed on the board eliminates lead damage on
high–pin–count packages (e.g., QFP packages) due to device handling.
MAX 3000A devices can be reprogrammed after a system has already
shipped to the field. For example, product upgrades can be performed in
the field via software or modem.
f
The Jam STAPL programming and test language can be used to program
MAX 3000A devices with in–circuit testers, PCs, or embedded processors.
For more information on using the Jam STAPL programming and test
language, see Application Note 88 (Using the Jam Language for ISP & ICR via
an Embedded Processor), Application Note 122 (Using Jam STAPL for ISP &
ICR via an Embedded Processor) and AN 111 (Embedded Programming Using
the 8051 and Jam Byte-Code).
The ISP circuitry in MAX 3000A devices is compliant with the IEEE Std.
1532 specification. The IEEE Std. 1532 is a standard developed to allow
concurrent ISP between multiple PLD vendors.
12 Altera Corporation

12 Page





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