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PDF AD6677 Data sheet ( Hoja de datos )
| Número de pieza | AD6677 | |
| Descripción | IF Receiver | |
| Fabricantes | Analog Devices | |
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Data Sheet
80 MHz Bandwidth,
IF Receiver
AD6677
FEATURES
GENERAL DESCRIPTION
JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
Signal-to-noise ratio (SNR) = 71.9 dBFS at 185 MHz AIN and
250 MSPS with noise shaping requantizer (NSR) set to 33%
Spurious-free dynamic range (SFDR) = 87 dBc at 185 MHz AIN
and 250 MSPS
Total power consumption: 435 mW at 250 MSPS
1.8 V supply voltages
Integer 1-to-8 input clock divider
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 400 MHz
Internal analog-to-digital converter (ADC) voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer (DCS)
Serial port control
Energy saving power-down modes
APPLICATIONS
Communications
Diversity radio and smart antenna multiple input, multiple
output (MIMO) systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
General-purpose software radios
The AD6677 is an 11-bit, 250 MSPS, intermediate frequency
(IF) receiver specifically designed to support multi-antenna
systems in telecommunication applications where high dynamic
range performance, low power, and small size are desired.
The device consists of a high performance ADC and a noise
shaping requantizer (NSR) digital block. The ADC consists of a
multistage, differential pipelined architecture with integrated
output error correction logic, and each ADC features a wide
bandwidth switched capacitor sampling network within the first
stage of the differential pipeline. An integrated voltage reference
eases design considerations. A duty cycle stabilizer compensates for
variations in the ADC clock duty cycle, allowing the converters
to maintain excellent performance.
The ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance
in a smaller frequency band within the Nyquist bandwidth.
The device supports two different output modes selectable via
the SPI. With the NSR feature enabled, the output of the ADC
is processed such that the AD6677 supports enhanced SNR
performance within a limited portion of the Nyquist bandwidth
while maintaining an 11-bit output resolution.
FUNCTIONAL BLOCK DIAGRAM
AVDD DRVDD DVDD AGND DGND DRGND
AD6677
VIN+
VIN–
VCM
PIPELINE
11-BIT ADC
NOISE
SHAPING
REQUANTIZER
(NSR)
JESD204B
INTERFACE
HIGH
SPEED
SERIALIZERS
CML, TX
OUTPUTS
SERDOUT0±
SYSREF±
SYNCINB±
CLK±
RFCLK
CONTROL
REGISTERS
CMOS
DIGITAL
INPUT
CLOCK
GENERATION
CMOS DIGITAL FAST
INPUT/OUTPUT DETECT
CMOS
DIGITAL
OUTPUT
PDWN
FD
RST SDIO SCLK CS
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD6677
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range,
duty cycle stabilizer enabled, default SPI, unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE-RATIO (SNR)
NSR Disabled
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
NSR Enabled 22% Bandwidth Mode
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
NSR Enabled 33% Bandwidth Mode
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
Temperature
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
Min Typ
Max Unit
66.6
66.4
66.2
66.1
65.8
65.9
76.3
75.7
74.8
74.2
73.6
73.6
73.5
72.1
72.6
71.9
70.6
71.4
65.6
65.3
65.2
65.1
64.7
64.8
10.6
10.6
10.5
10.5
10.5
−87
−82
−86
−87
−84
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
−80 dBc
dBc
Rev. B | Page 5 of 48
5 Page 
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD6677
RFCLK 1
CLK– 2
CLK+ 3
AVDD 4
SYSREF+ 5
SYSREF– 6
AVDD 7
RST 8
AD6677
TOP VIEW
(Not to Scale)
24 DNC
23 PDWN
22 CS
21 SCLK
20 SDIO
19 FD
18 DGND
17 DVDD
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF
THE PACKAGE PROVIDES THE GROUND REFERENCE FOR
AVDD. THIS EXPOSED PAD MUST BE CONNECTED TO AGND
FOR PROPER OPERATION.
Figure 4. Pin Configuration (Top View)
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
ADC Power Supplies
4, 7, 26, 27, 30, 31, 32
AVDD
9, 18 DGND
10, 17
DVDD
13 DRGND
14 DRVDD
Type
Supply
Ground
Supply
Ground
Supply
24 DNC
EPAD (AGND) Ground
ADC Analog
1
2
3
25
28
29
ADC Fast Detect Output
19
Digital Inputs
5
6
11
12
Data Outputs
15
16
RFCLK
CLK−
CLK+
VCM
VIN−
VIN+
Input
Input
Input
Output
Input
Input
FD Output
SYSREF+
SYSREF−
SYNCINB+
SYNCINB−
Input
Input
Input
Input
SERDOUT0−
SERDOUT0+
Output
Output
Description
Analog Power Supply (1.8 V Nominal).
Ground Reference for DVDD.
Digital Power Supply (1.8 V Nominal).
Ground Reference for DRVDD.
JESD204B PHY Serial Output Driver Supply (1.8 V Nominal). Note
that the DRVDD power is referenced to the AGND plane.
Do Not Connect.
Expose Pad. The exposed thermal pad on the bottom of the package
provides the ground reference for AVDD. This exposed pad must be
connected to AGND for proper operation.
ADC RF Clock Input.
ADC Nyquist Clock Input—Complement.
ADC Nyquist Clock Input—True.
Common-Mode Level Bias Output for Analog Inputs. Decouple this
pin to ground using a 0.1 µF capacitor.
Differential Analog Input (−).
Differential Analog Input (+).
Fast Detect Indicator (CMOS Levels).
JESD204B LVDS SYSREF Input—True.
JESD204B LVDS SYSREF Input—Complement.
JESD204B LVDS Sync Input—True/JESD204B CMOS Sync Input.
JESD204B LVDS Sync Input—Complement.
CML Output Data—Complement.
CML Output Data—True.
Rev. B | Page 11 of 48
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD6677.PDF ] | |
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