PDF AD9684 Data sheet ( Hoja de datos )

Número de pieza	AD9684
Descripción	Dual Analog-to-Digital Converter
Fabricantes	Analog Devices
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Data Sheet 14-Bit, 500 MSPS LVDS, Dual Analog-to-Digital Converter AD9684 FEATURES Parallel LVDS (DDR) outputs 1.1 W total power per channel at 500 MSPS (default settings) SFDR = 85 dBFS at 170 MHz fIN (500 MSPS) SNR = 68.6 dBFS at 170 MHz fIN (500 MSPS) ENOB = 10.9 bits at 170 MHz fIN DNL = ±0.5 LSB INL = ±2.5 LSB Noise density = −153 dBFS/Hz at 500 MSPS 1.25 V, 2.50 V, and 3.3 V supply operation No missing codes Internal analog-to-digital converter (ADC) voltage reference Flexible input range and termination impedance 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential SYNC± input allows multichip synchronization DDR LVDS (ANSI-644 levels) outputs 2 GHz usable analog input full power bandwidth >96 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation Two integrated wideband digital processors per channel 12-bit numerically controlled oscillator (NCO) 3 cascaded half-band filters Differential clock inputs Serial port control Integer clock divide by 2, 4, or 8 Small signal dither APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, MC-GSM, LTE General-purpose software radios Ultrawideband satellite receiver Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions) Radar Digital oscilloscopes High speed data acquisition systems DOCSIS CMTS upstream receiver paths HFC digital reverse path receivers FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 DVDD DRVDD (1.25V) (2.5V) (3.3V) (1.25V) (1.25V) SPIVDD (1.8V TO 3.4V) BUFFER VIN+A VIN–A ADC 14 CORE FD_A DIGITAL DOWN- CONVERTER 16 FD_B BUFFER VIN+B VIN–B V_1P0 CLK+ CLK– ADC 14 CORE DIGITAL DOWN- CONVERTER CONTROL REGISTERS CLOCK GENERATION FAST DETECT SIGNAL MONITOR SPI CONTROL ÷2 ÷4 AD9684 ÷8 D0± D1± D2± D3± D4± D5± D6± D7± D8± D9± D10± D11± D12± D13± DCO± STATUS± SYNC+ SYNC– PDWN/ STBY AGND DRGND DGND SDIO SCLK CSB Figure 1. GENERAL DESCRIPTION The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9684 is optimized for wide input bandwidth, a high sampling rate, excellent linearity, and low power in a small package. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs, supporting a variety of user selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate by 2 block. The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and three half-band decimation filters supporting a divide by factor of two, four, and eight. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet AD9684 AC SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (500 MSPS), 1.7 V p-p full-scale differential input, 1.0 V internal reference, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted. Table 2. Parameter1 ANALOG INPUT FULL SCALE NOISE DENSITY2 SIGNAL-TO-NOISE RATIO (SNR)3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz SIGNAL-TO-NOISE RATIO AND DISTORTION RATIO (SINAD)3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR)3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz WORST HARMONIC, SECOND OR THIRD3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz Temperature Full Full Min 25°C Full 67.5 25°C 25°C 25°C 25°C 25°C 25°C Full 67 25°C 25°C 25°C 25°C 25°C 25°C Full 10.8 25°C 25°C 25°C 25°C 25°C 25°C Full 76 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C Typ 2.06 −153 Max 69.2 68.6 68.4 68.0 64.4 63.8 60.5 68.7 68.5 67.6 67.2 63.8 62.5 58.3 11.1 10.9 10.8 10.8 10.3 10.1 9.5 83 85 82 86 81 76 69 −83 −85 −76 −82 −86 −81 −76 −69 Unit V p-p dBFS/Hz dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits Bits Bits Bits Bits dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Rev. 0 \| Page 5 of 64 5 Page Data Sheet AD9684 VIN±x APERTURE DELAY N N+x N + 36 N + 37 N + 38 SYNC+ SYNC– CLK+ CLK– DCO± (DATA CLOCK OUTPUT) 0° PHASE ADJUST SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET CONSTANT LATENCY = X CLK CYCLES tDCO tPD tCLK DCO± (DATA CLOCK OUTPUT) 180° PHASE ADJUST STATUS BIT SELECTED BY REGISTER 0x559, BITS[2:0] IN THE REGISTER MAP STATUS+ (OVERRANGE/STAUS BIT) STATUS– STATUS STATUS tSKEWR tSKEWF CONVERTERS SAMPLE [N] CONVERTERS SAMPLE [N] CONVERTERS SAMPLE [N + 1] CONVERTERS SAMPLE [N + 1] CONVERTERS SAMPLE [N + 2] STATUS STATUS STATUS STATUS STATUS STATUS CHANNEL A D12±/D13± CHANNEL A D0±/D1± S[N – y] S[N – x] (ODD BITS) (EVEN BITS) S[N – 1] S[N] S[N] S[N + 1] S[N + 1] S[N + 2] (ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS) (ODD BITS) (EVEN BITS) Figure 6. Channel Multiplexed (Even/Odd) Mode—One Converter, ≤14-Bit Data Rev. 0 \| Page 11 of 64 11 Page

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