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PDF STC89LE52RC Data sheet ( Hoja de datos )
| Número de pieza | STC89LE52RC | |
| Descripción | MCU | |
| Fabricantes | STC MCU | |
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STC89Cxx series MCU
STC89LExx series MCU
Data Sheet
1 page  
1.2 Block diagram
The CPU kernel of STC89xx series are fully compatible to the standard 8051 microcontroller, maintains all
instruction mnemonics and binary compatibility. STC89xx series can execute the fastest instructions per 6 clock
cycles or 12 clock cycles(as the same as the standard 80C51) . Improvement of individual programs depends on
the actual instructions used.
AUX-RAM
1024 Byte
RAM ADDR
Register
256 Byte
RAM
B Register
ACC
TMP2
TMP1
ALU
PSW
Stack
Poniter
Timer 0/1
Timer 2
UART
WDT
PSEN
ALE
EA
RESET
Control
Unit
XTAL1
XTAL2
Port 0,1,2,3,4
Latch
Port 0,1,2,3,4
Driver
P0, P1,P2,P3,P4
STC89xx Block Diagram
FLASH
64K
ISP/IAP
Address
Generator
Program
Counter
5 Page 
Chapter 2 POWER MANAGENMENT, RESET
2.1 Power Management
There are two power saving modes, which are selectable to drive the STC89xx enter power-saving mode by set-
ting the following SFR PCON.
PCON register (Power Control Register)
LSB
bit B7 B6 B5 B4 B3 B2 B1 B0
name SMOD SMOD0 -
POF GF1 GF0 PD IDL
SMOD : Double baud rate of UART interface
0 Keep normal baud rate when the UART is used in mode 1,2 or 3. (defaut)
1 Double baud rate bit when the UART is used in mode 1,2 or 3.
SMOD0 : SM0/FE bit select for SCON.7; setting this bit will set SCON.7 as Frame Error function. Clearing it to
set SCON.7 as one bit of UART mode selection bits.
B5 : Reserved
POF : Power-On flag. It is set by power-off-on action and can only cleared by software.
GF1 : General-purposed flag 1
GF0 : General-purposed flag 0
PD : Power-Down bit.
IDL : Idle mode bit.
2.1.1 Idle Mode
An instruction that sets IDL/PCON.0 causes that to be the last instruction executed before going into the idle
mode, the internal clock is gated off to the CPU but not to the interrupt, timer, WDT and serial port functions. The
CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator,
and all other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle
was activated. ALE and PSEN hold at logic high levels. Idle mode leaves the peripherals running in order to allow
them to wake up the CPU when an interrupt is generated. Timer 0, Timer 1, Timer 2 and UART will continue to
function during Idle mode.
There are two ways to terminate the idle. Activation of any enabled interrupt will cause IDL/PCON.0 to be
cleared by hardware, terminating the idle mode. The interrupt will be serviced, and following RETI, the next
instruction to be executed will be the one following the instruction that put the device into idle.
The flag bits (GFO and GF1) can be used to give art indication if an interrupt occurred during normal operation
or during Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is
terminated by an interrupt, the interrupt service routine can examine the flag bits.
The other way to wake-up from idle is to pull RESET high to generate internal hardware reset.Since the clock
oscillator is still running, the hardware reset neeeds to be held active for only two system clock cycles(24 system
clock) to complete the reset.
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