4 Mbit LPC Flash
SST49LF040B
FEATURES:
SST49LF040B4Mb LPC Flash memory
Advance Information
• 4 Mbit SuperFlash Memory Array for Code or
Data Storage
– SST49LF040B: 512K x8 (4 Mbit)
• Conforms to Intel LPC Interface Specification
– Supports Single-Byte LPC Memory Cycle
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 64 KByte overlay blocks
– Chip-Erase for PP Mode Only
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time: 8 seconds (typical)
– Single-pulse Program or Erase
– Internal timing generation
• Two Operational Modes
– Low Pin Count (LPC) interface mode for
in-system operation
– Parallel Programming (PP) mode for fast
production programming
• LPC Interface Mode
– LPC bus interface supporting byte Read and
Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write
protection for entire chip and/or top Boot Block
– Block Locking Registers for individual block
Write-Lock and Lock-Down protection
– JEDEC Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Write
detection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
• Parallel Programming (PP) Mode
– 11-pin multiplexed address and 8-pin data
I/O interface
– Supports fast In-System or PROM programming
for manufacturing
• CMOS and PCI I/O Compatibility
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST49LF040B flash memory devices are designed to
interface with host controllers (chipsets) that support a low-
pin-count (LPC) interface for BIOS code storage. Two inter-
face modes are supported by the SST49LF040B: LPC
Memory mode for in-system operation compatible with
Intel’s LPC Interface Specification and Parallel Program-
ming (PP) mode to interface with industry-standard pro-
gramming equipment.
The SST49LF040B flash memory devices are manufac-
tured with SST’s proprietary, high-performance SuperFlash
technology. The split-gate cell design and thick-oxide tun-
neling injector attain greater reliability and manufacturability
compared with alternative approaches. The
SST49LF040B devices significantly improve performance
and reliability, while lowering power consumption. The
SST49LF040B devices write (Program or Erase) with a
single 3.0-3.6V power supply.
The SST49LF040B use less energy during Erase and Pro-
gram than alternative flash memory technologies. The total
energy consumed is a function of the applied voltage, cur-
rent and time of application. Since for any given voltage
range the SuperFlash technology uses less current to pro-
gram and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less than
alternative flash memory technologies.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. This means the system software
or hardware does not have to be calibrated or correlated to
the cumulative number of Erase cycles as is necessary
with alternative flash memory technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
©2006 Silicon Storage Technology, Inc.
S71226-03-000
5/06
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
Intel is a registered trademark of Intel Corporation.
These specifications are subject to change without notice.
Advance Information
LPC Memory Read Cycle
4 Mbit LPC Flash
SST49LF040B
TABLE 3: LPC Memory Read Cycle Field Definitions
Clock
Cycle
Field
Name
Field Contents LAD[3:0]
LAD[3:0]1
Direction Comments
1 START 0000
IN LFRAME# must be active (low) for the device to respond. Only
the last field latched before LFRAME# transitions high will be
recognized. The START field contents (0000b) indicate an LPC
Memory cycle.
2 CYCTYPE 010X
+ DIR
IN Indicates the type of LPC Memory cycle. Bits 3:2 must be “01b” for
memory cycle. Bit 1 indicates the type of transfer “0” for Read. Bit 0 is
reserved.
3-10
ADDR
YYYY
IN Address Phase for Memory Cycle. LPC protocol supports a 32-
bit address phase. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
11 TAR0
1111
IN In this clock cycle, the host drives the bus to all 1s and then
then Float floats the bus. This is the first part of the bus “turnaround cycle.”
12
TAR1
1111 (float)
Float
The SST49LF040B takes control of the bus during this cycle.
then OUT
13 SYNC
0000
OUT
The SST49LF040B outputs the value 0000b indicating that it
has received data.
14 DATA
ZZZZ
OUT
ZZZZ is the least-significant nibble of the data byte.
15 DATA
ZZZZ
OUT
ZZZZ is the most-significant nibble of the data byte.
16 TAR0
1111
OUT
then Float
In this clock cycle, the SST49LF040B drives the bus to all 1s
and then floats the bus. This is the first part of the bus “turn-
around cycle.”
17
TAR1
1111 (float)
Float
The host takes control of the bus during this cycle.
then IN
1. Field contents are valid on the rising edge of the present clock cycle.
T3.0 1226
LCLK
LFRAME#
LAD[3:0]
CYCTYPE
Start
+
DIR
Address
0000b 010Xb A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8]
1 Clock 1 Clock
Load Address in 8 Clocks
A[7:4]
A[3:0]
TAR0 TAR1 Sync
Data
1111b Tri-State 0000b D[3:0] D[7:4]
2 Clocks
1 Clock Data Out 2 Clocks
FIGURE 5: LPC Memory Read Cycle Waveform
TAR
1226 F05.1
©2006 Silicon Storage Technology, Inc.
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S71226-03-000
5/06
