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ADuM1402 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADuM1402
Beschreibung Quad-Channel Digital Isolators
Hersteller Analog Devices
Logo Analog Devices Logo 



Gesamt 30 Seiten
		
ADuM1402 Datasheet, Funktion
Data Sheet
Quad-Channel Digital Isolators
ADuM1400/ADuM1401/ADuM1402
FEATURES
GENERAL DESCRIPTION
Qualified for automotive applications
The ADuM1400/ADuM1401/ADuM14021 are quad-channel
Low power operation
digital isolators based on Analog Devices, Inc., iCoupler®
5 V operation
technology. Combining high speed CMOS and monolithic air
1.0 mA per channel maximum at 0 Mbps to 2 Mbps
core transformer technology, these isolation components provide
3.5 mA per channel maximum at 10 Mbps
outstanding performance characteristics superior to alternatives,
31 mA per channel maximum at 90 Mbps
such as optocoupler devices.
3 V operation
0.7 mA per channel maximum at 0 Mbps to 2 Mbps
2.1 mA per channel maximum at 10 Mbps
20 mA per channel maximum at 90 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 125°C
High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics
2 ns maximum pulse width distortion
2 ns maximum channel-to-channel matching
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with opto-
couplers. The typical optocoupler concerns regarding uncertain
current transfer ratios, nonlinear transfer functions, and
temperature and lifetime effects are eliminated with the simple
iCoupler digital interfaces and stable performance characteristics.
The need for external drivers and other discrete components is
eliminated with these iCoupler products. Furthermore, iCoupler
devices consume one tenth to one sixth of the power of
optocouplers at comparable signal data rates.
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body package
RoHS-compliant models available
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak
TÜV approval: IEC/EN/UL/CSA 61010-1
The ADuM1400/ADuM1401/ADuM1402 isolators provide four
independent isolation channels in a variety of channel configu-
rations and data rates (see the Ordering Guide). All models
operate with the supply voltage on either side ranging from
2.7 V to 5.5 V, providing compatibility with lower voltage
systems as well as enabling a voltage translation functionality
across the isolation barrier. In addition, the ADuM1400/
ADuM1401/ADuM1402 provide low pulse width distortion
(<2 ns for CRW grade) and tight channel-to-channel matching
(<2 ns for CRW grade). Unlike other optocoupler alternatives, the
ADuM1400/ADuM1401/ADuM1402 isolators have a patented
APPLICATIONS
General-purpose multichannel isolation
SPI interface/data converter isolation
refresh feature that ensures dc correctness in the absence of input
logic transitions and when power is not applied to one of the
supplies.
RS-232/RS-422/RS-485 transceivers
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
Industrial field bus isolation
Automotive systems
FUNCTIONAL BLOCK DIAGRAMS
VDD1 1
GND1 2
VIA 3
VIB 4
VIC 5
VID 6
NC 7
GND1 8
ENCODE
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DECODE
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Figure 1. ADuM1400
16 VDD2
15 GND2
14 VOA
13 VOB
12 VOC
11 VOD
10 VE2
9 GND2
VDD1 1
GND1 2
VIA 3
VIB 4
VIC 5
VOD 6
VE1 7
GND1 8
ENCODE
ENCODE
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DECODE
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Figure 2. ADuM1401
16 VDD2
15 GND2
14 VOA
13 VOB
12 VOC
11 VID
10 VE2
9 GND2
VDD1 1
GND1 2
VIA 3
VIB 4
VOC 5
VOD 6
VE1 7
GND1 8
ENCODE
ENCODE
DECODE
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Figure 3. ADuM1402
16 VDD2
15 GND2
14 VOA
13 VOB
12 VIC
11 VID
10 VE2
9 GND2
Rev. K
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






ADuM1402 Datasheet, Funktion
ADuM1400/ADuM1401/ADuM1402
Data Sheet
ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION1
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. These specifications do not apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 2.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM1400 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1401 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 or VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 or VDD2 Supply Current
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM1400ARW/ADuM1401ARW/ADuM1402ARW
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching7
Symbol
IDDI (Q)
IDDO (Q)
Min
Typ Max Unit Test Conditions
0.26 0.31 mA
0.11 0.14 mA
IDD1 (Q)
IDD2 (Q)
IDD1 (10)
IDD2 (10)
IDD1 (90)
IDD2 (90)
1.2 1.9 mA DC to 1 MHz logic signal freq.
0.5 0.9 mA DC to 1 MHz logic signal freq.
4.5 6.5 mA 5 MHz logic signal freq.
1.4 2.0 mA 5 MHz logic signal freq.
37 65 mA 45 MHz logic signal freq.
11 15 mA 45 MHz logic signal freq.
IDD1 (Q)
IDD2 (Q)
IDD1 (10)
IDD2 (10)
IDD1 (90)
IDD2 (90)
1.0 1.6 mA DC to 1 MHz logic signal freq.
0.7 1.2 mA DC to 1 MHz logic signal freq.
3.7 5.4 mA 5 MHz logic signal freq.
2.2 3.0 mA 5 MHz logic signal freq.
30 52 mA 45 MHz logic signal freq.
18 27 mA 45 MHz logic signal freq.
IDD1 (Q), IDD2 (Q)
0.9 1.5 mA DC to 1 MHz logic signal freq.
I , IDD1 (10) DD2 (10)
3.0 4.2 mA 5 MHz logic signal freq.
I , IDD1 (90) DD2 (90)
24 39 mA 45 MHz logic signal freq.
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH,
VOCH, VODH
VOAL, VOBL,
VOCL, VODL
−10 +0.01 +10 µA
1.6
(VDD1 or VDD2) − 0.1
(VDD1 or VDD2) − 0.4
3.0
2.8
0.0
0.04
0.2
0.4
0.1
0.1
0.4
V
V
V
V
V
V
V
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
PW
tPHL, tPLH
PWD
1
50
tPSK
tPSKCD/tPSKOD
1000 ns CL = 15 pF, CMOS signal levels
Mbps CL = 15 pF, CMOS signal levels
75 100 ns CL = 15 pF, CMOS signal levels
40 ns CL = 15 pF, CMOS signal levels
11 ps/°C CL = 15 pF, CMOS signal levels
50 ns CL = 15 pF, CMOS signal levels
50 ns CL = 15 pF, CMOS signal levels
Rev. K | Page 6 of 31

6 Page







ADuM1402 pdf, datenblatt
ADuM1400/ADuM1401/ADuM1402
Data Sheet
Parameter
ADuM1400WTRWZ/ADuM1401WTRWZ/
ADuM1402WTRWZ
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional
Channels7
Channel-to-Channel Matching, Opposing-
Directional Channels7
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
Output Enable Propagation Delay (High
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at Logic
High Output8
Common-Mode Transient Immunity at Logic
Low Output8
Refresh Rate
Input Dynamic Supply Current per Channel9
Output Dynamic Supply Current per Channel9
Symbol
PW
tPHL, tPLH
PWD
tPSK
tPSKCD
tPSKOD
tPHZ, tPLH
tPZH, tPZL
tR/tF
|CMH|
|CML|
fr
IDDI (D)
IDDO (D)
Min
10
18
25
25
Typ Max Unit
Test Conditions
100 ns
Mbps
27 32 ns
3 ns
5 ps/°C
15 ns
3 ns
6 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
68
68
2.5
35
35
1.2
0.19
0.05
ns CL = 15 pF, CMOS signal levels
ns CL = 15 pF, CMOS signal levels
ns CL = 15 pF, CMOS signal levels
kV/µs
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
kV/µs
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Mbps
mA/Mbps
mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. K | Page 12 of 31

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