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PDF EM639165TS Data sheet ( Hoja de datos )
| Número de pieza | EM639165TS | |
| Descripción | 8M x 16 bit Synchronous DRAM | |
| Fabricantes | Etron Technology | |
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EtronTech
EM639165TS
Etron Confidential
8M x 16 bit Synchronous DRAM (SDRAM)
Advanced (Rev 1.0, Mar. /2009)
Features
• Fast access time from clock: 5/5.4 ns
• Fast clock rate: 166/143 MHz
• Fully synchronous operation
• Internal pipelined architecture
• 2M word x 16-bit x 4-bank
• Programmable Mode registers
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
• Auto Refresh and Self Refresh
• 4096 refresh cycles/64ms
• CKE power down mode
• Single +3.3V ± 0.3V power supply
• Interface: LVTTL
• 54-pin 400 mil plastic TSOP II package
- Pb free and Halogen free
Overview
The EM639165 SDRAM is a high-speed CMOS
synchronous DRAM containing 128 Mbits. It is
internally configured as 4 Banks of 2M word x 16
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal,
CLK). Read and write accesses to the SDRAM are
burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with
the registration of a BankActivate command which
is then followed by a Read or Write command.
The EM639165 provides for programmable
Read or Write burst lengths of 1, 2, 4, 8, or full page,
with a burst termination option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh are easy to use.
By having a programmable mode register, the
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth and particularly well suited to high
performance PC applications.
Table1. Key Specifications
EM639165
tCK3 Clock Cycle time(min.)
tAC3 Access time from CLK(max.)
tRAS Row Active time(min.)
tRC Row Cycle time(min.)
- 6/7
6/7 ns
5/5.4 ns
42/42 ns
60/63 ns
Table 2. Ordering Information
Part Number
Frequency
EM639165TS -6G 166MHz
Package
TSOP II
EM639165TS -7G 143MHz
TSOP II
TS: indicates TSOPII Package,
G: indicates Pb and Halogen Free for TSOPII Package
Figure 1. Pin Assignment (Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE#
CAS#
RAS#
CS#
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS
53 DQ15
52 VSSQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 VSSQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 VSS
40 NC/RFU
39 UDQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc. reserves the right to change products or specification without notice.
1 page  
EtronTech
EM639165TS
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 4
shows the truth table for the operation commands.
Table 4. Truth Table (Note (1), (2))
Command
State CKEn-1 CKEn DQM BA0,1 A10 A0-9,11 CS# RAS# CAS# WE#
BankActivate
Idle(3)
H
X X V Row address L L H H
BankPrecharge
Any H X X V L X L L H L
PrechargeAll
Any H X X X H X L L H L
Write
Write and AutoPrecharge
Active(3)
Active(3)
H
H
X V V L Column L H L
address
X V V H (A0 ~ A8) L H L
L
L
Read
Read and Autoprecharge
Active(3)
Active(3)
H
H
X V V L Column L H L H
address
X V V H (A0 ~ A8) L H L H
Mode Register Set
Idle H X X
OP code
LL L L
No-Operation
Any H X X X X X L H H H
Burst Stop
Active(4) H X X X X X L H H L
Device Deselect
Any H X X X X X H X X X
AutoRefresh
Idle H H X X X X L L L H
SelfRefresh Entry
Idle H L X X X X L L L H
SelfRefresh Exit
Idle L H X X X X H X X X
(SelfRefresh)
LH H H
Clock Suspend Mode Entry
Active H L X X X X H X X X
LV V V
Power Down Mode Entry
Any(5)
H
L X XX
X
HX X X
LH H H
Clock Suspend Mode Exit
Active L H X X X X X X X X
Power Down Mode Exit
Any L H X X X X H X X X
(PowerDown)
LH H H
Data Write/Output Enable
Active H X L X X X X X X X
Data Mask/Output Disable
Active H X H X X X X X
Note:
1. V=Valid, X=Don't Care L=Low level H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
X
X
Etron Confidential
5 Rev 1.0 Mar. 2009
5 Page 
EtronTech
EM639165TS
CLK
T0 T1 T2 T3 T4 T5 T6 T7
DQM
COMMAND WRITE NOP
NOP
Precharge
tRP
NOP
NOP
Activate NOP
ADDRESS
DQ
BANK
COL n
DIN
N
tWR
DIN
N+1
BANK(S)
ROW
Don’t Care
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Figure 13. Write to Precharge
7 Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H", A0-A8
= Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after the
write operation. Once this command is given, any subsequent command can not occur within a time
delay of {(burst length -1) + tWR + tRP (min.)}. At full-page burst, only the write operation is performed in
this command and the auto precharge function is ignored.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
CLK
COMMAND
Bank A
Activate
NOP
DQ
tDAL=tWR+tRP
NOP
Write A
Auto Precharge
NOP
DIN A0 DIN A1
NOP NOP
tDAL
NOP
NOP
Bank A
Activate
Begin AutoPrecharge
Bank can be reactivated at
completion of tDAL
Figure 14. Burst Write with Auto-Precharge (Burst Length = 2)
8 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The Mode
Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in the
Mode register to make SDRAM useful for a variety of different applications. The default values of the
Mode Register after power-up are undefined; therefore this command must be issued at the power-up
sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to the mode register.
Two clock cycles are required to complete the write in the mode register (refer to the following figure).
The contents of the mode register can be changed using the same command and the clock cycle
requirements during operation as long as all banks are in the idle state.
Etron Confidential
11 Rev 1.0 Mar. 2009
11 Page | ||
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