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ADV7481 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV7481
Beschreibung Integrated Video Decoder and Dual Mode HDMI/MHL Receiver
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 22 Seiten
ADV7481 Datasheet, Funktion
Data Sheet
Integrated Video Decoder and
Dual Mode HDMI/MHL Receiver
ADV7481
FEATURES
Analog input
Worldwide NTSC/PAL/SECAM color demodulation support
with autodetection
One 10-bit ADC, 4× oversampling for CVBS, Y/C, and YPbPr
8 analog video input channels with on-chip antialiasing filter
Fully differential, pseudo differential, and single-ended
CVBS video input support
STB diagnostics on differential video inputs
CVBS (composite), Y/C (S-Video), and YPbPr (component)
video input support
Fast switching capability between analog inputs
Adaptive contrast enhancement (ACE)
Excellent common-mode noise rejection capabilities
Rovi (Macrovision) copy protection detection
Up to 4 V common-mode input range solution
Vertical blanking interval (VBI) data slicer
Mobile High-Definition Link (MHL) capable receiver
High-bandwidth Digital Content Protection (HDCP)
authentication and decryption support
75 MHz maximum pixel clock frequency, allowing HDTV
formats up to 720p/1080i at 60 Hz
24 bits per pixel mode supported
HDCP repeater support, up to 25 KSVs supported
Adaptive TMDS equalizer
High-Definition Multimedia Interface (HDMI) capable
receiver
HDCP authentication and decryption support
162 MHz maximum pixel clock frequency, allowing HDTV
formats up to 1080p and display resolutions up to UXGA
(1600 × 1200 at 60 Hz)
HDCP repeater support, up to 25 KSVs supported
Integrated CEC controller, CEC 1.4 compatible
Adaptive TMDS equalizer
5 V detect and Hot Plug assert
Component video processor
Any-to-any 3 × 3 color space conversion (CSC) matrix
Contrast/brightness/hue/saturation video adjustment
Timing adjustments controls for horizontal sync
(HS)/vertical sync (VS)/data enable (DE) timing
Video mute function
Serial digital audio output interface
HDMI/MHL audio extraction support
Advanced audio muting feature
I2S-compatible, left justified, and right justified audio
output modes
8-channel TDM output mode available
2 Mobile Industry Processor Interface (MIPI) Camera Serial
Interface 2 (CSI-2) transmitters
4-lane transmitter with 4 lanes, 2 lanes, and 1 lane muxing
options for HDMI/MHL/SDP/digital input port sources
1-lane transmitter for standard definition processor (SDP)
sources
8-bit digital input/output port
General
2-wire serial microprocessor unit (MPU) interface (I2C
compatible)
−40°C to +85°C temperature grade
100-ball, 9 mm × 9 mm, RoHS-compliant CSP_BGA package
Qualified for automotive applications
APPLICATIONS
Portable devices
Automotive infotainment (head unit and rear seat
entertainment systems)
HDMI repeaters and video switches
FUNCTIONAL BLOCK DIAGRAM
RXCP/RXCN
RX0P/RX0N
RX1P/RX1N
RX2P/RX2N
DDC_SCL/
CD_PULLU P
DDC_SD A
HPD/CBUS
CD_SENSE
CEC
RX_5V/VBUS
VBUS_EN
LLC
P0 TO P7
AIN1 TO
AIN8
DIAG1 TO
DIAG4
MHL_SENSE
CBUS
DDC
HDMI/MHL
RECEIVER
CEC
HPD
EDID RAM
HDCP
8-BIT TTL
INPUT/OUTPUT
ADV7481
AUDIO
PROCESSOR
CP
CORE
AFE
SD
CORE
DIAGNOSTIC
SPI SLAVE
I2C SLAVE
INTERRUPTS
CONTROLLER
AUDIO OUTPUT
FORMATTER
4-LANE
MIPI CSI-2
TRANSMITTER
1-LANE
MIPI CSI-2
TRANSMITTER
SPI_MISO
SPI_MOSI
SPI_SCLK
SPI_CS
ALSB
SCLK
SDATA
INTRQ1 TO
INTRQ3
I2S_MCLK
I2S_LRCLK
I2S_SCLK
I2S_SDATA
CLKAP/CLKAN
DA0P/DA0N TO
DA3P/DA3N
CLKBP/CLKBN
DB0P/DB0N
Figure 1.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






ADV7481 Datasheet, Funktion
ADV7481
Parameter
HDMI/MHL Terminator Supply Current
Single-Ended CVBS Input
Fully Differential and Pseudo
Differential CVBS Input
Y/C Input
YPbPr Input
HDMI Input
MHL Input
8-Bit Digital Input
HDMI/MHL Comparator Supply Current
Single-Ended CVBS Input
Fully Differential and Pseudo
Differential CVBS Input
Y/C Input
YPbPr Input
HDMI Input
MHL Input
8-Bit Digital Input
PLL Supply Current
Single-Ended CVBS Input
Fully Differential and Pseudo
Differential CVBS Input
Y/C Input
YPbPr Input
HDMI Input
MHL Input
8-Bit Digital Input
MIPI Transmitters Supply Current
Single-Ended CVBS Input
Fully Differential and Pseudo
Differential CVBS Input
Y/C Input
YPbPr Input
HDMI Input
MHL Input
8-Bit Digital Input
Digital Input/Output Supply Current
Single-Ended CVBS Input
Fully Differential and Pseudo
Differential CVBS Input
Y/C Input
YPbPr Input
HDMI Input
MHL Input
8-Bit Digital Input
Analog Supply Current
Single-Ended CVBS Input
Fully Differential and Pseudo
Differential CVBS Input
Y/C Input
YPbPr Input
HDMI Input
MHL Input
8-Bit Digital Input
Symbol
ITVDD
ICVDD
IPVDD
IMVDD
IDVDDIO
IAVDD
Test Conditions/Comments
Rev. 0 | Page 6 of 22
Data Sheet
Min Typ
0.7
0.7
Max Unit
40 mA
mA
mA
0.7
0.7
35
24.4
0.7
92
0.1
0.1
mA
mA
mA
mA
mA
mA
mA
mA
0.1
0.1
63.9
55.9
0.1
52
37.5
37.5
mA
mA
mA
mA
mA
mA
mA
mA
37.7
37.7
29.2
29.3
27.9
77
23.3
23.3
mA
mA
mA
mA
mA
mA
mA
mA
23.2
23.2
45.7
38.5
38.1
78
0.2
0.2
mA
mA
mA
mA
mA
mA
mA
mA
0.2
0.2
3.6
0.6
0.2
93
51.9
70
mA
mA
mA
mA
mA
mA
mA
mA
63 mA
78.5 mA
0.1 mA
0.1 mA
0.1 mA

6 Page









ADV7481 pdf, datenblatt
ADV7481
LLC
t21 t22 t23
P7 TO P0
Figure 7. 8-Bit Digital Pixel Video Input, SDR Video Data Timing
LLC
t21
t23
t22
t24
t25
P7 TO P0
Figure 8. 8-Bit Digital Pixel Video Input, DDR Video Data Timing
t26
LLC
P7 TO P0
t36
t37
Figure 9. 8-Bit Digital Pixel Video Output, SDR Video Data Timing
LLC
t26
P7 TO P0
t27
t28
t29
t30
I2S_SCLK
I2S_LRCLK
I2S_SDATA
LEFT JUSTIFIED
MODE
I2S_SDATA
I2S MODE
I2S_SDATA
RIGHT JUSTIFIED
MODE
Figure 10. 8-Bit Digital Pixel Video Output, DDR Video Data Timing
t31
t32
t33
t34
MSB
MSB – 1
t35 t34
MSB
MSB – 1
t35
MSB
Figure 11. I2S Timing
t34
t35
LSB
Data Sheet
Rev. 0 | Page 12 of 22

12 Page





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