PDF EN25Q32 Data sheet ( Hoja de datos )

Número de pieza	EN25Q32
Descripción	32 Megabit Serial Flash Memory
Fabricantes	Eon Silicon Solution
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EN25Q32 EN25Q32 32 Megabit Serial Flash Memory with 4Kbyte Uniform Sector FEATURES • Single power supply operation - Full voltage range: 2.7-3.6 volt • 32 M-bit Serial Flash - 32 M-bit/4096 K-byte/16384 pages - 256 bytes per programmable page • Standard, Dual or Quad SPI - Standard SPI: CLK, CS#, DI, DO, WP#, HOLD# - Dual SPI: CLK, CS#, DQ0, DQ1, WP#, HOLD# - Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3 • High performance - 100MHz clock rate for one data bit - 80MHz clock rate for two data bits - 80MHz clock rate for four data bits • Low power consumption - 5 mA typical active current - 1 μA typical power down current • Uniform Sector Architecture: - 1024 sectors of 4-Kbyte - 64 blocks of 64-Kbyte - Any sector or block can be erased individually • Individual Block Protect/Unprotect Feature - Protect/Unprotect Blocks Command • Software and Hardware Write Protection: - Write Protect all or portion of memory via software - Enable/Disable protection with WP# pin • High performance program/erase speed - Page program time: 1.5ms typical - Sector erase time: 150ms typical - Block erase time 800ms typical - Chip erase time: 25 Seconds typical • Lockable 512 byte OTP security sector • Minimum 100K endurance cycle • Package Options - 8 pins SOP 200mil body width - 8 contact VDFN - All Pb-free packages are RoHS compliant • Industrial temperature Range GENERAL DESCRIPTION The EN25Q32 is a 32 Megabit (4096K-byte) Serial Flash memory, with advanced write protection mechanisms. The EN25Q32 supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O using SPI pins: Serial Clock, Chip Select, Serial DQ0(DI), DQ1(DO), DQ2(WP#) and DQ3(HOLD#). SPI clock frequencies of up to 80MHz are supported allowing equivalent clock rates of 160MHz for Dual Output and 320MHz for Quad Output when using the Dual/Quad Output Fast Read instructions. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The EN25Q32 also offers a sophisticated method for protecting individual blocks against erroneous or malicious program and erase operations. By providing the ability to individually protect and unprotect blocks, a system can unprotect a specific block to modify its contents while keeping the remaining blocks of the memory array securely protected. This is useful in applications where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. The EN25Q32 is designed to allow either single Sector at a time or full chip erase operation. The EN25Q32 can be configured to protect part of the memory as the software protected mode. The device can sustain a minimum of 100K program/erase cycles on each sector. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 1 ©2004 Eon Silicon Solution, Inc., Rev. A, Issue Date: 2008/09/18 www.eonssi.com 1 page Table 1. Pin Names Symbol CLK DI (DQ0) DO (DQ1) CS# WP# (DQ2) HOLD# (DQ3) Vcc Vss NC Pin Name Serial Clock Input Serial Data Input (Data Input Output 0) 1 Serial Data Output (Data Input Output 1) 1 Chip Enable Write Protect (Data Input Output 2) 2 Hold Input (Data Input Output 3) 2 Supply Voltage (2.7-3.6V) Ground No Connect Note: 1. DQ0 and DQ1 are used for Dual and Quad instructions. 2. DQ0 ~ DQ3 are used for Quad instructions. EN25Q32 MEMORY ORGANIZATION The memory is organized as: z 4,194,304 bytes z Uniform Sector Architecture 64 blocks of 64-Kbyte 1024 sectors of 4-Kbyte z 16384 pages (256 bytes each) Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector, Block or Chip Erasable but not Page Erasable. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 5 ©2004 Eon Silicon Solution, Inc., Rev. A, Issue Date: 2008/09/18 www.eonssi.com 5 Page EN25Q32 Write Protection Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern the EN25Q32 provides the following data protection mechanisms: z Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. z Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events: – Power-up – Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction completion or Page Program (PP) instruction completion or Sector Erase (SE) instruction completion or Block Erase (BE) instruction completion or Chip Erase (CE) instruction completion z The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). z The Write Protect (WP#) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM). z In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the Release from Deep Power-down instruction). Table 3. Protected Area Sizes Sector Organization Status Register Content BP2 BP1 BP0 Bit Bit Bit 000 001 010 011 100 101 110 111 Memory Content Protect Blocks None Block 63 Block 62 to 63 Block 60 to 63 Block 56 to 63 Block 48 to 63 Block 32 to 63 All Addresses None 3F0000h-3FFFFFh 3E0000h-3FFFFFh 3C0000h-3FFFFFh 380000h-3FFFFFh 300000h-3FFFFFh 200000h-3FFFFFh 000000h-3FFFFFh Density(KB) None 64KB 128KB 256KB 512KB 1024KB 2048KB 4096KB Portion None Upper 1/64 Upper 1/32 Upper 1/16 Upper 1/8 Upper 1/4 Upper 1/2 All Hold Function The Hold (HOLD#) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold condition starts on the falling edge of the Hold (HOLD#) signal, provided that this coincides with Serial Clock (CLK) being Low (as shown in Figure 4.). The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided that this coincides with Serial Clock (CLK) being Low. If the falling edge does not coincide with Serial Clock (CLK) being Low, the Hold condition starts after Serial Clock (CLK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (CLK) being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in Figure 4.). During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are Don’t Care. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 11 ©2004 Eon Silicon Solution, Inc., Rev. A, Issue Date: 2008/09/18 www.eonssi.com 11 Page

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