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PDF A7102A Data sheet ( Hoja de datos )

Número de pieza A7102A
Descripción 315/433MHz FSK Transceiver
Fabricantes AMICCOM 
Logotipo AMICCOM Logotipo



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No Preview Available ! A7102A Hoja de datos, Descripción, Manual

Amiccom
Preliminary
www.avantcom.com.tw
A7102A
315/433MHz FSK Transceiver
Document Title
315/433 MHz FSK Transceiver
Revision History
Rev. No.
0.0
0.1
History
Initial issue.
Logo changed.
Issue Date
July 18th, 2007
Nov. 5th, 2007
Remark
Preliminary
Important Notice:
AMICCOM reserves the right to make changes to its products or to discontinue any integrated circuit product or service
without notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable
for use in life-support applications, devices or systems or other critical applications. Use of AMICCOM products in such
applications is understood to be fully at the risk of the customer.
Nov. 2007, Version 0.1 (PRELIMINARY)
Amiccom
www.avantcom.com.cn
AMIC Communication Corporation

1 page




A7102A pdf
Amiccom
www.avantcom.com.tw
A7102A
Preliminary
315/433MHz FSK Transceiver
7. Pin Descriptions (I: input; O: output; OD: open drain output)
Pin No.
Symbol
Function Description
1
RSSI
O RSSI bypass. Connect to external capacitor.
2
VSS
I Analog ground.
3 RFI I RF input.
4
VSS
I Analog ground.
5
RFO
O RF output.
6
VSS
I Analog ground.
7
VSS
I Analog ground.
8
VDD_VCO
I VCO Supply voltage.
9
VCON
I VCO inductor negative connection pin
10 VCOP I VCO inductor positive connection pin
11 VT I Control voltage of VCO
12
CPO
O Charge-pump output. This pin charges external capacitor to adjust VCO frequency.
VDD_P
PLL Supply voltage.
13 LL I
14 XO I Crystal oscillator node 2. Connect to external feedback capacitor.
15 XI I Crystal oscillator node 1. Connect to external feedback capacitor.
16
VDD_DIG
O Digital supply voltage. Connect to bypass capacitor.
17 SCS I SPI chip select. Active low.
18 SCK I SPI/FIFO clock.
19
SDIO
IO SPI/FIFO data.
20 DIO IO Bi-directional pin for direct mode. DATA input/output for TX/RX
21
CKO
O Clock out. Can be configured to RCK (RX recovery clock) or DCK (TX data clock).
22
IRQ
O
Interrupt request. Can be configured to CD (carrier detect), SYNC (RX frame sync) or
FP (FIFO packet).
23 TRS I TX/RX mode select. 0: RX, 1: TX.
24 TRE I TX/RX mode enable pin. Active high.
25 PWR_ON I Chip power on pin. Active high.
26 REG_IN I 3.3V supply voltage input pin.
27
RTCO
O 32KHz clock output.
28 XO_32K I 32KHz crystal oscillator node 2. Connect to external feedback capacitor.
29 XI_32K I 32KHz crystal oscillator node 1. Connect to external feedback capacitor.
30
BP_BG
O Bandgap bypass pin. Connect to external capacitor.
31
VDD_A
O Analog Supply voltage. Connect to bypass capacitor.
32 ADC_IN I External input for on-chip ADC.
Nov. 2007, Version 0.1 (PRELIMINARY)
Amiccom
4
www.avantcom.com.cn
AMIC Communication Corporation

5 Page





A7102A arduino
Amiccom
www.avantcom.com.tw
A7102A
Preliminary
315/433MHz FSK Transceiver
CRCS: CRC select. 1: Select. The CRC is CCITT-16 CRC.
FECS: FEC select. 1: Select. The FEC is (7, 4) Hamming code.
WHTS: Data whitening select. 1: Select. The data is whitening by multiplying PN7.
MCS: Manchester code select. 1: Select.
WS [6:0]: Whitening seed.
Address 0Dh: Pin Control
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
PCS IRQI IRQ1 IRQ0 IRQE CKOI CKO1 CKO0 CKOE SCKI
R/W W W W W W W W W W W
Reset
0000000 1 0 1
SCKI: SPI clock invert. 1: Invert.
CKOE: CKO pin output enable. 0: High Z, 1: Enable.
CKO [1:0]: CKO select.
[00]: BCK (bit clock).
[01]: MRCK (modulation rate).
[10]: FPF (FIFO pointer flag).
[11]: Reversed.
When Manchester code is selected, BCK is the bit clock of Manchester code that equals half modulation rate.
In such case, BCK will appear after TX modulation start in TX mode or internal frame sync in RX mode. On the
other hand, BCK equals modulation rate.
When [11] selected, the output is the logic OR of EOP, EOVBC, EOFBC, EOADC and OKADC.
CKOI: CKO invert. 1: Invert.
IRQE: IRQ pin output enable. 0: High Z, 1: Enable.
IRQ [1:0]: IRQ function select.
TX state
[00] WPLL state & TX state(WTR)
[01] End of Access code (EOAC)
[10] TX modulation enable (TMEO)
[11] None
RX state
WPLL state & RX state(WTR)
Access code matched (FSYNC)
carrier detected (CD)
External FSYNC input ( for direct mode)
When IRQ set to [11] and direct mode is selected, the internal frame sync function will be disabled. In such case, it is
recommended that user assure frame sync signal to this input to get better DC estimation of demodulation.
IRQI: IRQ output invert. 0: normal, 1: Invert.
PCS: TRE and TRS pin control. 0: Register control, 1: Pin control.
Address 0Eh: Calibration
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
VTL2 VTL1 VTL0 VTH2 VTH1 VTH0 MVBS MVB2 MVB1 MVB0 MFBS MFB3 MFB2 MFB1 MFB0
R/W W W W W W W W W W W W W W W W
Reset
0 000000 1 0 0 0 0 1 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FCD4 FCD3 FCD2 FCD1 FCD0 DVT1 DVT0 VBCF VB2 VB1 VB0 FBCF FB3 FB2 FB1 FB0
R/W R R R R R R R R R R R R R R R R
Reset
MFB [3:0]: Manual IF filter bank setting.
MFBS: Manual IF filter bank select. 0: FB, 1: MFB.
MVB [2:0]: Manual VCO bank setting. VCO frequency increases when MVB decreases.
MVBS: Manual VCO band select. 0: VB, 1: MVB.
VTH [2:0]: VT high threshold setting for VCO calibration.
[000]Æ VTH=Vdd-0.1V [100]Æ VTH=Vdd-0.5V
[001]Æ VTH=Vdd-0.2V [101]Æ VTH=Vdd-0.6V
[010]Æ VTH=Vdd-0.3V [110]Æ VTH=Vdd-0.7V
[011]Æ VTH=Vdd-0.4V [111]Æ VTH=Vdd-0.8V
VTL [2:0]: VT low threshold setting for VCO calibration.
[000]Æ VTL=0.1V [100]Æ VTL=0.5V
[001]Æ VTL=0.2V [101]Æ VTL=0.6V
[010]Æ VTL=0.3V [110]Æ VTL=0.7V
[011]Æ VTL=0.4V [111]Æ VTL=0.8V
Nov. 2007, Version 0.1 (PRELIMINARY)
Amiccom
10
www.avantcom.com.cn
AMIC Communication Corporation

11 Page







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