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PDF A5841 Data sheet ( Hoja de datos )
| Número de pieza | A5841 | |
| Descripción | BiMOS II 8-Bit Serial Input Latched Driver | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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A5841
BiMOS II 8-Bit Serial Input Latched Driver
Discontinued Product
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: October 31, 2005
Recommended Substitutions:
For new customers or new applications, refer to the A6841.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a
product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information
included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor
for any infringements of patents or other rights of third parties which may result from its use.
1 page  
5841
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
TYPICAL INPUT CIRCUITS
VDD
STROBE
OUTPUITN
ENABLE
CLOCK
SERIAL
DATA IN
Dwg. EP-010-3
VDD
Dwg. EP-010-4A
TYPICAL OUTPUT DRIVER
K
OUT
V
EE
SUB
Dwg. EP-021-8
CLOCK
DATA IN
STROBE
OUTPUT
ENABLE
OUTN
AD
B
E
C
F
G
Dwg. No. A-12,627
TIMING CONDITIONS
(TA = +25°C, VDD = 5.0 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
D. Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
E. Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . . 300 ns
F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ns
G. Typical Time Between Strobe Activation and
Output Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 µs
Serial Data present at the input is transferred to the shift register
on the logic “0” to logic “1” transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective
latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is held
high. Applications where the latches are bypassed (STROBE tied high)
will require that the ENABLE input be high during serial data entry.
When the ENABLE input is high, all of the output buffers are
disabled (OFF) without affecting the information stored in the latches or
shift register. With the ENABLE input low, the outputs are controlled by
the state of the latches.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet A5841.PDF ] | |
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