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34708 Schematic ( PDF Datasheet ) - Freescale Semiconductor

Teilenummer 34708
Beschreibung Power Management Integrated Circuit
Hersteller Freescale Semiconductor
Logo Freescale Semiconductor Logo 




Gesamt 30 Seiten
34708 Datasheet, Funktion
Freescale Semiconductor
Technical Data
Power Management Integrated
Circuit (PMIC) for i.MX50/53
Families
MC34708
Rev. 11.0, 11/2013
34708
The MC34708 is the Power Management Integrated Circuit (PMIC)
designed specifically for use with the Freescale i.MX50 and i.MX53
families. This device is powered by SMARTMOS technology.
Features
• Six multi-mode buck regulators for direct supply of the processor
core, memory, and peripherals
• Boost regulator for USB OTG support
• Eight regulators with internal and external pass devices for thermal
budget optimization
• USB/UART/Audio switching for mini-micro USB connector
• 10-bit ADC for monitoring battery and other inputs
• Real time clock and crystal oscillator circuitry with coin cell backup/
charger
• SPI/I2C bus for control and register interface
POWER MANAGEMENT
VK SUFFIX (PB-FREE)
98ASA00312D
206 MAPBGA
8.0 X 8.0 (0.5 MM PITCH)
VM SUFFIX (PB-FREE)
98ASA00299D
206 MAPBGA
13.0 X 13.0 (0.8 MM PITCH)
Applications
Tablets
Smart Mobile Devices
Portable Navigation Devices

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Figure 1. MC34708 Simplified Application Diagram
There are no disclaimers required on the Final publication of a data sheet.
© Freescale Semiconductor, Inc., 2011-2013. All rights reserved.






34708 Datasheet, Funktion
3 Internal Block Diagram
3.1 Simplified Internal Diagram
Internal Block Diagram
Input/Battery
Monitoring
GNDADC
ADIN9
ADIN10
ADIN11
ADIN12/TSX1
ADIN13/TSX2
ADIN14/TSY1
ADIN15/TSY2
TSREF
BPTHERM
NTCREF
Voltage /
Current
Sensing &
Translation
LICELL, UID, Die Temp, GPO4
10 Bit GP
ADC
A/D Result
MUX
A/D
Control
Touch
Screen
Interface
General Purpose
LED Drivers
DVS
CONTROL
Die Temp &
Thermal Warning
Detection
To Interrupt
Section
SW1
Dual Phase
GP
2000 mA
Buck
SW2
100L0`PmA
Buck
SW3
INT MEM
500 mA
Buck
BATTISNSCCP
BATTISNSCCN
CFP
CFN
SPIVCC
CS
CLK
MOSI
MISO
GNDSPI
SPI
Interface
+
Muxed
I2C
Optional
Interface
Shift Register
SPI
Registers
Shift Register
To Enables & Control
Package Pin Legend
Output Pin
Input Pin
Bi-directional Pin
VALWAYS
VCORE
VCOREDIG
VDDLP
VCOREREF
GNDCORE
GNDREF
SPKR
SPKL
MIC
TXD
RXD
DPLUS
DMINUS
DP
DM
GNDUSB
UID
VBUS
VINUSB
VUSB
LICELL
Reference
Generation
VBUS/ID
Detectors, Host
Auto detection
UART Switches
Audio Switches
OVP
VUSB
Regulator
BP
Li Cell
Charger
LCELL
Switch
32 KHz
Internal
Osc
32 KHz
Crystal
Osc
MC34708
SPI
Control
Logic
Trim-In-Package
PUMSx
Startup
Sequencer
Decode
Trim?
To
Trimmed
Circuits
Control
Logic
SPI Result
Registers
Interrupt
Inputs
Enables &
Control
Core Control LDoiggiitca,l CTiomreers, & Interrupts
SW4
Dual Phase
DDR
1000 mA
Buck
SW5
I/O
1000 mA
Buck
SWBST
380 mA
Boost
SPI Control
VREFDDR
10mA
VPLL
50 mA
VUSB2
350mA
VDAC
250mA
VGEN1
250mA
PLL
Monitor
Timer
RTC +
Calibration
32 KHz
Buffers
Switchers
Best
of
Supply
VSRTC
VGEN2
250mA
GPIO Control
O/P
Drive
O/P
Drive
SW1IN
SW1ALX
GNDSW1A
SW1FB
SW1CFG
SW1VSSSNS
SW1BLX
GNDSW1B
SW1PWGD
O/P
Drive
SW2IN
SW2LX
GNDSW2
SW2FB
SW2PGD
O/P
Drive
O/P
Drive
O/P
Drive
O/P
Drive
SW3IN
SW3LX
GNDSW3
SW3FB
SW4AIN
SW4ALX
GNDSW4A
SW4AFB
SW4CFG
SW4BIN
SW4BLX
GNDSW4B
SW4BFB
SW5IN
SW5LX
GNDSW5
SW5FB
O/P
Drive
SWBSTIN
SWBSTLX
SWBSTFB
GNDSWBST
Pass
FET
Pass
FET
VINREFDDR
VHALF
VREFDDR
VINPLL
VPLL
VUSB2DRV
VUSB2
VDACDRV
VDAC
Pass
FET
VINGEN1
VGEN1
Pass
FET
VGEN2DRV
VGEN2
LDOVDD
PWM
Outputs
GNDREG1
GNDREG2
GNDREF1
GNDREF2
Figure 2. Simplified Internal Block Diagram
Analog Integrated Circuit Device Data
Freescale Semiconductor
MC34708
6

6 Page









34708 pdf, datenblatt
Pin Connections
Table 3. MC34708 Pin Definitions (continued)
Pin Number Pin Name
Pin
Function
Definition
D4
F2
USB (2)
SDWNB
GNDSPI
O
GND
Indication of imminent system shutdown
Ground for SPI interface
H3 UID I/O USB OTG transceiver cable ID
L3
GNDUSB
GND USB Ground
K1 DP I/O USB Data +
J1 DM I/O USB Data –
L1
DPLUS
I/O Processor D+
M1
DMINUS
I/O Processor D-
G4 RXD O UART Receive
G5
TXD
I/O UART Transmit
H7 MIC O Mic output
J2 SPKR I Speaker right
K2 SPKL I Speaker left
H1
VBUS
I/O USB transceiver cable interface VBUS & OTG supply output
H2 VUSB O USB transceiver regulator output
G3 VINUSB
I Input option for VUSB; tie to SWBST at top level.
A to D Converter
K7 ADIN9 I ADC generic input channel 9
K6 ADIN10
I ADC generic input channel 10,
L6 ADIN11 I ADC generic input channel 11
K4 TSX1/ADIN12 I Touch Screen Interface X1 or ADC generic input channel 12
L5 TSX2/ADIN13 I Touch Screen Interface X2 or ADC generic input channel 13
J7 TSY1/ADIN14 I Touch Screen Interface Y1 or ADC generic input channel 14
J6 TSY2/ADIN15 I Touch Screen Interface Y2 or ADC generic input channel 15
P1 TSREF O Touch Screen Reference
N2, N3, N4,
P3, P4
GNDADC
GND Ground for ADC
Thermal Grounds
H5
SUBSREF
GND Substrate ground connection for reference circuitry
E9, F8,F9,
L7, G9, H6,
H8, H9, J8,
J9, K8, K9
K15
SUBSPWR1
SUBSLDO
GND Substrate ground connection for power devices SW1, SW4, SW5
GND Substrate ground connection for all LDOs
N13
SUBSANA1
GND Substrate ground connection for analog circuitry of SW1, SW4, SW5
B15
SUBSANA2
GND Substrate ground connection for analog circuitry of SW2, SW3, SWBST
Analog Integrated Circuit Device Data
Freescale Semiconductor
MC34708
12

12 Page





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