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AD7641 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7641
Beschreibung 18-Bit 2 MSPS SAR ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 28 Seiten
AD7641 Datasheet, Funktion
FEATURES
Throughput
2 MSPS (wideband warp and warp mode)
1.5 MSPS (normal mode)
INL: ±2 LSB typical, ±3 LSB max; ±8 ppm of full scale
18-bit resolution with no missing codes
Dynamic range: 95.5 dB
SNR: 93.5 dB typical @ 20 kHz (VREF = 2.5 V)
THD: −112 dB typical @ 20 kHz (VREF = 2.5 V)
2.048 V internal reference: typ drift 10 ppm/°C; TEMP output
Differential input range: ±VREF (VREF up to 2.5 V)
No pipeline delay (SAR architecture)
Parallel (18-, 16-, or 8-bit bus) and
serial 5 V/3.3 V/2.5 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Single 2.5 V supply operation
Power dissipation
75 mW typical @ 2 MSPS with internal REF
2 μW in power-down mode
Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ
Speed upgrade of the AD7674, AD7678, AD7679
APPLICATIONS
Medical instruments
High speed data acquisition/high dynamic data acquisition
Digital signal processing
Spectrum analysis
Instrumentation
Communications
ATE
GENERAL DESCRIPTION
The AD7641 is an 18-bit, 2 MSPS, charge redistribution SAR,
fully differential, analog-to-digital converter (ADC) that
operates from a single 2.5 V power supply. The part contains a
high speed, 18-bit sampling ADC, an internal conversion clock,
an internal reference (and buffer), error correction circuits, and
both serial and parallel system interface ports. It features two
very high sampling rate modes (wideband warp and warp) and
a fast mode (normal) for asynchronous rate applications. The
AD7641 is hardware factory calibrated and tested to ensure ac
parameters, such as signal-to-noise ratio (SNR), in addition to
the more traditional dc parameters of gain, offset, and linearity.
The AD7641 is available in Pb-free only packages with
operation specified from −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
18-Bit, 2 MSPS SAR ADC
AD7641
FUNCTIONAL BLOCK DIAGRAM
TEMP REFBUFIN REF REFGND
DVDD DGND
AGND
AVDD
IN+
IN–
PDREF
PDBUF
PD
RESET
REF
REF AMP
SWITCHED
CAP DAC
AD7641
SERIAL
PORT 18
PARALLEL
INTERFACE
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
OVDD
OGND
D[17:0]
MODE0
MODE1
BUSY
RD
CS
D0/OB/2C
WARP NORMAL CNVST
Figure 1.
Table 1. PulSAR® Selection
Type/kSPS
100 to
250
Pseudo
Differential
AD7651,
AD7660,
AD7661
True Bipolar
True
Differential
AD7610,
AD7663
AD7675
500 to
570
AD7650,
AD7652,
AD7664,
AD7666
AD7665
AD7676
18-Bit
Multichannel/
Simultaneous
AD7631,
AD7678
AD7679
AD7654
650 to
1000
AD7653,
AD7667
AD7612,
AD7671
AD7677
AD7634,
AD7674
AD7655
>1000
AD7621,
AD7622,
AD7623
AD7641,
AD7643
PRODUCT HIGHLIGHTS
1. Fast Throughput.
The AD7641 is a 2 MSPS, charge redistribution,
18-bit SAR ADC.
2. Superior Linearity.
The AD7641 has no missing 18-bit code.
3. Internal Reference.
The AD7641 has a 2.048 V internal reference with a typical
drift of ±10 ppm/°C and an on-chip TEMP sensor.
4. Single-Supply Operation.
The AD7641 operates from a 2.5 V single supply.
5. Serial or Parallel Interface.
Versatile parallel (16- or 8-bit bus) or 2-wire serial interface
arrangement compatible with 2.5 V, 3.3 V, or 5 V logic.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.






AD7641 Datasheet, Funktion
AD7641
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
DIVSCLK[0]
Symbol
SYNC to SCLK First Edge Delay Minimum
t18
Internal SCLK Period Minimum
t19
Internal SCLK Period Maximum
t19
Internal SCLK High Minimum
t20
Internal SCLK Low Minimum
t21
SDOUT Valid Setup Time Minimum
t22
SDOUT Valid Hold Time Minimum
t23
SCLK Last Edge to SYNC Delay Minimum
t24
BUSY High Width Maximum
t24
0
0
0.5
8
14
2
3
1
0
0
0.630
0
1
3
16
26
6
7
5
0.5
0.5
0.870
1
0
3
32
52
15
16
5
10
9
1.350
1
1 Unit
3 ns
64 ns
103 ns
31 ns
32 ns
5 ns
28 ns
26 ns
2.28 μs
500µA
IOL
TO OUTPUT
PIN CL
50pF
1.4V
500µA
IOH
NOTE
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, CL = 10 pF
0.8V
tDELAY
2V
0.8V
2V
tDELAY
2V
0.8V
Figure 3. Voltage Reference Levels for Timing
Rev. 0 | Page 6 of 28

6 Page









AD7641 pdf, datenblatt
AD7641
TYPICAL PERFORMANCE CHARACTERISTICS
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0
65536
131072
CODE
196608
262144
Figure 5. Integral Nonlinearity vs. Code
40000
35000
30000
25000
34844
31003
24739
σ = 1.55
20000
15000
10000
10938
5000
4730
11 683
002
0
272
16207
5248
2124
232 39 0 0
CODE IN HEX
Figure 6. Histogram of 261,120 Conversions of a DC Input at
the Code Center (External Reference)
2.0530
2.0525
2.0520
2.0515
2.0510
2.0505
2.0500
2.0495
2.0490
2.0485
2.0480
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
Figure 7. Typical Reference Voltage Output vs. Temperature (3 Units)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
30000
25000
20000
65536
131072
196608
CODE
Figure 8. Differential Nonlinearity vs. Code
262144
24731
22225 23436
18995
σ = 2.02
15000
10000
12922
10846
5000
2105
912
1 1 52 117
0
8219
4688
1171
58951 10 1
CODE IN HEX
Figure 9. Histogram of 261,120 Conversions of a DC Input at
the Code Center (Internal Reference)
20
18
16 –FS
14
12
10
8
6
4
2
0
–2
–4 ZERO-ERROR
–6
–8
–10
–12
–14
–16 +FS
–18
–20
–55 –35 –15 5
25 45 65 85 105 125
TEMPERATURE (°C)
Figure 10. Zero Error, Positive and Negative Full Scale vs. Temperature
Rev. 0 | Page 12 of 28

12 Page





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