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71M6545H Schematic ( Datenblatt PDF ) - Maxim

Teilenummer 71M6545H
Beschreibung Metrology Processors
Hersteller Maxim
Logo Maxim Logo 



Gesamt 30 Seiten
		
71M6545H Datasheet, Funktion
71M6545/71M6545H
Metrology Processors
GENERAL DESCRIPTION
The 71M6545/71M6545H metrology processors are based on
4th-generation metering architecture supporting the 71M6xxx
series of isolated current sensing products that offer drastic
reduction in component count, immunity to magnetic tampering,
and unparalleled reliability. The 71M6545/71M6545H integrate
our Single Converter Technology® with a 22-bit delta-sigma
ADC, a customizable 32-bit computation engine (CE) for core
metrology functions, as well as a user-programmable 8051-
compatible application processor (MPU) core with up to 64KB
flash and up to 5KB RAM.
An external host processor can access metrology functions di-
rectly through the SPI™ interface, or alternatively through the
embedded MPU core in applications requiring metrology data
capture, storage, and preprocessing within the metrology
subsystem. In addition, the devices integrate an RTC, DIO, and
UART. A complete array of ICE and development tools,
programming libraries, and reference designs enable rapid
development and certification of meters that meet all ANSI and
IEC electricity metering standards worldwide.
C Shunt Resistor Sensors
NEUTRAL
B
A
LOAD
HOST
POWER SUPPLY
This system is referenced to Neutral
NEUTRAL
Pulse Transformers
C
B
A
SPI_CKI
SPI_DI
SPI_DO
SPI_CSZ
XFER_BUSY
SAG
MUX and ADC
IADC0
IADC1
} IN*
VADC10 (VC)
IADC6
IADC7
}
IC
VADC9 (VB)
IADC4
IADC5
}
IB
VADC8(VA)
IADC2
IADC3
} IA
V3P3A V3P3SYS GNDA GNDD
PWR MODE
CONTROL
71M6545/H
PB
REGULATOR
TEMPERATURE
SENSOR
VBAT_RTC
BATTERY
MONITOR
VREF
SERIAL PORT
RX
TX
FLASH
MEMORY
RAM
MPU
RTC
TIMERS
OSCILLATOR/
PLL XIN
XOUT
DIO, PULSES,
LEDs
DIO
ICE
T
SPI INTERFACE
M
U
COMPUTE
ENGINE
X
V3P3D
WPULSE
XPULSE
RPULSE
YPULSE
10/7/2010
RTC
BATTERY
32 kHz
24
DIO
I2C or µWire
EEPROM
PULSES 3.3 VDC
*IN = Optional Neutral Current
FEATURES
0.1% Typical Accuracy Over 2000:1
Current Range
Exceeds IEC 62053/ANSI C12.20 Standards
Seven Sensor Inputs with Neutral Current
Measurement, Differential Mode Selectable
for Current Inputs
Selectable Gain of 1 or 8 for One Current
Input to Support Shunts
High-Speed Wh/VARh Pulse Outputs with
Programmable Width
Flash/RAM Size
32KB/3KB (71M6545)
64KB/5KB (71M6545H)
Up to Four Pulse Outputs with Pulse Count
Four-Quadrant Metering, Phase
Sequencing
Digital Temperature Compensation
Metrology Compensation
Accurate RTC for TOU Functions with
Automatic Temperature Compensation
for Crystal in All Power Modes
Independent 32-Bit Compute Engine
46–64Hz Line Frequency Range with the
Same Calibration
Phase Compensation (±7°)
1µA Supply Current in Sleep Mode
Flash Security
In-System Program Update
8-Bit MPU (80515), Up to 5 MIPS, for
Optional Implementation of Postprocessing
and Host Support Functions (Optional Use)
Up to 29 DIO Pins
Hardware Watchdog Timer (WDT)
I2C/MICROWIRE® EEPROM Interface
SPI Interface for Host:
Full Access to Shared Memory Space
Flash Program Capability
UART
Industrial Temperature Range
64-Pin Lead(Pb)-Free LQFP Package
Single Converter Technology is a registered trademark of Maxim Integrated Products, Inc.
MICROWIRE is a registered trademark of National Semiconductor Corp.
For pricing, delivery, and ordering information, please contact Maxim Direct at
19-5378; Rev 2; 10/13
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.






71M6545H Datasheet, Funktion
71M6545/71M6545H Data Sheet
PDS_6545_009
Tables
Table 1. Required CE Code and Settings for 1-Local / 3-Remotes ............................................................ 15
Table 2. Required CE Code and Settings for CT Sensors ......................................................................... 16
Table 3: Multiplexer and ADC Configuration Bits ...................................................................................... 19
Table 4. RCMD[4:0] Bits ............................................................................................................................. 22
Table 6: I/O RAM Control Bits for Isolated Sensor .................................................................................... 24
Table 7: Inputs Selected in Multiplexer Cycles ........................................................................................... 26
Table 8: CKMPU Clock Frequencies .......................................................................................................... 31
Table 9: Memory Map ................................................................................................................................. 32
Table 10: Internal Data Memory Map ......................................................................................................... 33
Table 11: Special Function Register Map ................................................................................................... 33
Table 12: Generic 80515 SFRs - Location and Reset Values .................................................................... 34
Table 13: PSW Bit Functions (SFR 0xD0) ................................................................................................... 35
Table 14: Port Registers (DIO0-14) ............................................................................................................ 36
Table 15: Stretch Memory Cycle Width ...................................................................................................... 36
Table 16: Baud Rate Generation ................................................................................................................ 37
Table 17: UART Modes............................................................................................................................... 37
Table 18: The S0CON (UART0) Register (SFR 0x98)................................................................................. 38
Table 19: PCON Register Bit Description (SFR 0x87) ................................................................................. 38
Table 20: Timers/Counters Mode Description ............................................................................................ 39
Table 21: Allowed Timer/Counter Mode Combinations .............................................................................. 39
Table 22: TMOD Register Bit Description (SFR 0x89)................................................................................ 39
Table 23: The TCON Register Bit Functions (SFR 0x88)............................................................................ 40
Table 24: The IEN0 Bit Functions (SFR 0xA8)............................................................................................ 41
Table 25: The IEN1 Bit Functions (SFR 0xB8)............................................................................................ 41
Table 26: The IEN2 Bit Functions (SFR 0x9A)............................................................................................ 41
Table 27: TCON Bit Functions (SFR 0x88) ................................................................................................. 41
Table 28: The T2CON Bit Functions (SFR 0xC8)....................................................................................... 42
Table 29: The IRCON Bit Functions (SFR 0xC0) ........................................................................................ 42
Table 30: External MPU Interrupts.............................................................................................................. 42
Table 31: Interrupt Enable and Flag Bits .................................................................................................... 43
Table 32: Interrupt Priority Level Groups .................................................................................................... 43
Table 33: Interrupt Priority Levels ............................................................................................................... 44
Table 34: Interrupt Priority Registers (IP0 and IP1) .................................................................................... 44
Table 35: Interrupt Polling Sequence.......................................................................................................... 44
Table 36: Interrupt Vectors.......................................................................................................................... 44
Table 37: Flash Memory Access................................................................................................................. 46
Table 38: Flash Security ............................................................................................................................. 47
Table 39: Clock System Summary.............................................................................................................. 49
Table 40: RTC Control Registers ................................................................................................................ 50
Table 41: I/O RAM Registers for RTC Temperature Compensation .......................................................... 51
Table 42: I/O RAM Registers for RTC Interrupts ........................................................................................ 53
Table 43: I/O RAM Registers for Temperature and Battery Measurement ................................................ 54
Table 44: Data/Direction Registers and Internal Resources for DIO0 to DIO14 ........................................ 55
Table 45: Data/Direction Registers for DIO19-25 and DIO28-29 ............................................................... 56
Table 46: Data/Direction Registers for DIO55 ............................................................................................ 56
Table 47: Selectable Resources using the DIO_Rn[2:0] Bits ..................................................................... 56
Table 48: EECTRL Bits for 2-pin Interface................................................................................................... 57
Table 49: EECTRL Bits for the 3-wire Interface ........................................................................................... 58
6 v2

6 Page







71M6545H pdf, datenblatt
71M6545/71M6545H Data Sheet
PDS_6545_009
correction factors can be programmed to produce electricity meters with exceptional accuracy over the
industrial temperature range.
One of the two internal UARTs is adapted to support an Infrared LED with internal drive and sense
configuration and can also function as a standard UART. This flexibility makes it possible to implement
AMR meters with an IR interface. A block diagram of the IC is shown in Figure 1.
2.2 Analog Front End (AFE)
The AFE functions as a data acquisition system, controlled by the MPU or by the host processor over the
SPI interface. The 71M6545/H AFE may also be augmented by isolated 71M6xx3 sensors in order to
support low-cost current shunt sensors. Figure 2 and Figure 3 show two of the most common
configurations; other configurations are possible. Sensors that are connected directly to the 71M6545/H
(i.e., IADC0-IADC1, VADC8, VADC9 and VADC10) are multiplexed into the single second-order sigma-
delta ADC input for sampling in the 71M6545/H. The 71M6545/H ADC output is decimated by the FIR
filter and stored in CE RAM where it can be accessed and processed by the CE.
Shunt current sensors that are isolated by using a 71M6xx3 device, are sampled by a second-order
sigma delta ADC in the 71M6xx3 and the signal samples are transferred over the digital isolation interface
through the low-cost isolation pulse transformer.
Figure 2 shows the 71M6545/H using shunt current sensors and the 71M6xx3 isolated sensor devices.
Figure 2 supports neutral current measurement with a local shunt connected to the IADC0-IADC1 input
plus three remote (isolated) shunt sensors. As seen in Figure 2, when a remote isolated shunt sensor is
connected via the 71M6xx3, the samples associated with this current channel are not routed to the
multiplexer, and are instead transferred digitally to the 71M6545/H via the isolation interface and are
directly stored in CE RAM. The MUX_SELn[3:0] I/O RAM control fields allow the MPU to configure the
AFE for the desired multiplexer sampling sequence. Refer to Table 1 and Table 2 for the appropriate CE
code and the corresponding AFE settings.
See Figure 27 for the meter wiring configuration corresponding to Figure 2.
IN*
Local
Shunt
IADC0
IADC1
VADC8 (VA)
MUX
VREF
VREF
VADC
∆Σ ADC
CONVERTER
VREF
FIR
22
VADC9 (VB)
IA
Remote
Shunt
INP SP
71M6xx3
SN
INN
IB
Remote
Shunt
INP SP
71M6xx3
SN
INN
VADC10 (VC)
IADC2
IADC3
IADC4
IADC5
Digital
Isolation
Interface
22
CE RAM
22
IC
INP SP
Remote
Shunt
71M6xx3
SN
INN
IADC6
IADC7
22
*IN = Neutral Current
71M6545/H
10/7/2010
Figure 2: AFE Block Diagram (Shunts: One-Local, Three-Remotes)
12 v2

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