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Teilenummer | CAV93C66 |
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Beschreibung | EEPROM | |
Hersteller | ON Semiconductor | |
Logo | ||
Gesamt 10 Seiten CAV93C66
4 Kb Microwire Serial CMOS
EEPROM
Description
The CAV93C66 is a 4 Kb CMOS Serial EEPROM device which is
organized as either 256 registers of 16 bits (ORG pin at VCC) or 512
registers of 8 bits (ORG pin at GND). Each register can be written (or
read) serially by using the DI (or DO) pin. The device features
sequential read and self−timed internal write with auto−clear. On−chip
Power−On Reset circuitry protects the internal logic against powering
up in the wrong state.
Features
• Automotive Temperature Grade 1 (−40°C to +125°C)
• High Speed Operation: 2 MHz
• 2.5 V to 5.5 V Supply Voltage Range
• Selectable x8 or x16 Memory Organization
• Self−timed Write Cycle with Auto−clear
• Sequential Read
• Software Write Protection
• Power−up Inadvertent Write Protection
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• 8−lead SOIC and TSSOP Packages
• These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
VCC
ORG
CS
SK
DI
CAV93C66
DO
GND
Figure 1. Functional Symbol
Note: When the ORG pin is connected to VCC, the x16 organization is
selected. When it is connected to ground, the x8 organization is
selected. If the ORG pin is left unconnected, then an internal pull−up
device will select the x16 organization.
http://onsemi.com
SOIC−8
V SUFFIX
CASE 751BD
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATIONS
CS 1
SK
DI
DO
VCC
NC
ORG
GND
SOIC (V), TSSOP (Y)
(Top View)
Pin Name
CS
SK
DI
DO
VCC
GND
ORG
NC
PIN FUNCTION
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
Memory Organization
No Connection
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
December, 2013 − Rev. P0
1
Publication Order Number:
CAV93C66/D
CAV93C66
Write
After receiving a WRITE command (Figure 5), address
and the data, the CS (Chip Select) pin must be deselected for
a minimum of tCSMIN. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the SK
pin is not necessary after the device has entered the self
clocking mode. The ready/busy status of the CAV93C66 can
be determined by selecting the device and polling the DO
pin. Since this device features Auto−Clear before write, it is
NOT necessary to erase a memory location before it is
written into.
Erase
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
tCSMIN (Figure 6). The falling edge of CS will start the self
clocking clear cycle of the selected memory location. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAV93C66 can be determined by selecting the device and
polling the DO pin. Once cleared, the content of a cleared
location returns to a logical “1” state.
SK
CS STANDBY
DI 1 0 0
* ENABLE = 11
DISABLE = 00
*
Figure 4. EWEN/EWDS Instruction Timing
SK
CS
AN AN−1
DI 1 0 1
tCSMIN
A0 DN
D0
STATUS
VERIFY
STANDBY
tSV BUSY
tHZ
DO HIGH−Z
READY HIGH−Z
tEW
Figure 5. Write Instruction Timing
SK
CS
AN AN−1
DI 1 1 1
A0 tCS
STATUS
VERIFY
STANDBY
DO
HIGH−Z
tSV
BUSY READY
tHZ
HIGH−Z
tEW
Figure 6. Erase Instruction Timing
http://onsemi.com
6
6 Page | ||
Seiten | Gesamt 10 Seiten | |
PDF Download | [ CAV93C66 Schematic.PDF ] |
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