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Teilenummer | CAV25010 |
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Beschreibung | EEPROM | |
Hersteller | ON Semiconductor | |
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Gesamt 12 Seiten CAV25010, CAV25020,
CAV25040
1-Kb, 2-Kb and 4-Kb SPI
Serial CMOS EEPROM
Description
The CAV25010/20/40 are 1−Kb/2−Kb/4−Kb Serial CMOS
EEPROM devices internally organized as 128x8/256x8/512x8 bits.
They feature a 16−byte page write buffer and support the Serial
Peripheral Interface (SPI) protocol. The device is enabled through a
Chip Select (CS) input. In addition, the required bus signals are a clock
input (SCK), data input (SI) and data output (SO) lines. The HOLD
input may be used to pause any serial communication with the
CAV25010/20/40 device. These devices feature software and
hardware write protection, including partial as well as full array
protection.
Features
• Automotive Temperature Grade 1 (−40°C to +125°C)
• 10 MHz SPI Compatible
• 2.5 V to 5.5 V Supply Voltage Range
• SPI Modes (0,0) & (1,1)
• 16−byte Page Write Buffer
• Self−timed Write Cycle
• Hardware and Software Protection
• Block Write Protection
− Protect 1/4, 1/2 or Entire EEPROM Array
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial and Extended Temperature Range
• SOIC and TSSOP 8−Lead Packages
• These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
VCC
SI
CS
WP
HOLD
SCK
CAV25010
CAV25020
CAV25040
SO
VSS
Figure 1. Functional Symbol
http://onsemi.com
SOIC−8
V SUFFIX
CASE 751BD
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATION
CS 1
SO
VCC
HOLD
WP SCK
VSS SI
SOIC (V), TSSOP (Y)
For the location of Pin 1, please consult the
corresponding package drawing.
Pin Name
CS
SO
WP
VSS
SI
SCK
HOLD
VCC
PIN FUNCTION
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
January, 2012 − Rev. 0
1
Publication Order Number:
CAV25010/D
CAV25010, CAV25020, CAV25040
Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 8−bit address
and data as shown in Figure 5. For the CAV25040, bit 3 of
the write instruction opcode contains A8 address bit.
Internal programming will start after the low to high CS
transition. During an internal write cycle, all commands,
except for RDSR (Read Status Register) will be ignored.
The RDY bit will indicate if the internal write cycle is in
progress (RDY high), or the device is ready to accept
commands (RDY low).
Page Write
After sending the first data byte to the CAV25010/20/40,
the host may continue sending data, up to a total of 16 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the
CAV25010/20/40 is automatically returned to the write
disable state.
CS
SCK
SI
012345678
13 14 15 16 17 18 19 20 21 22 23
00
OPCODE
0 0 X* 0 1
BYTE ADDRESS
DATA IN
0 A7
A0 D7 D6 D5 D4 D3 D2 D1 D0
SO HIGH IMPEDANCE
Dashed Line = mode (1, 1)
* X = 0 for CAV25010, CAV25020. x = A8 for CAV25040
Figure 5. Byte WRITE Timing
CS
SCK
012345678
13 14 15 16−23 24−31 16+(N−1)x8−1..16+(N−1)x8
16+Nx8−1
OPCODE
BYTEADDRESS
DATA IN
SI 0 0 0 0 X* 0 1 0 A7
A0
Data Data Data
Byte 1 Byte 2 Byte 3
SO HIGH IMPEDANCE
Dashed Line = mode (1, 1)
* X = 0 for CAV25010, CAV25020. x = A8 for CAV25040
Figure 6. Page WRITE Timing
Data Byte N
7..1 0
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6
6 Page CAV25010, CAV25020, CAV25040
ORDERING INFORMATION
Device Order
Number
Specific
Device
Marking
(Note 10)
Package Type
Temperature
Range
Lead Finish
Shipping
CAV25010VE−G
25010E
SOIC−8, JEDEC
−40°C to +125°C
NiPdAu
Tube, 100 Units / Tube
CAV25010VE−GT3
25010E
SOIC−8, JEDEC
−40°C to +125°C
NiPdAu
Tape & Reel, 3,000 Units / Reel
CAV25010YE−G
S01E
TSSOP−8
−40°C to +125°C
NiPdAu
Tube, 100 Units / Tube
CAV25010YE−GT3
S01E
TSSOP−8
−40°C to +125°C
NiPdAu
Tape & Reel, 3,000 Units / Reel
CAV25020VE−GT3
25020E
SOIC−8, JEDEC
−40°C to +125°C
NiPdAu
Tape & Reel, 3,000 Units / Reel
CAV25020YE−GT3
S02E
TSSOP−8
−40°C to +125°C
NiPdAu
Tape & Reel, 3,000 Units / Reel
CAV25040VE−G
25040E
SOIC−8, JEDEC
−40°C to +125°C
NiPdAu
Tube, 100 Units / Tube
CAV25040VE−GT3
25040E
SOIC−8, JEDEC
−40°C to +125°C
NiPdAu
Tape & Reel, 3,000 Units / Reel
CAV25040YE−GT3
S04E
TSSOP−8
−40°C to +125°C
NiPdAu
Tape & Reel, 3,000 Units / Reel
10. Specific Device Marking shows the first row top package marking.
11. All packages are RoHS−compliant (Lead−free, Halogen−free).
12. The standard lead finish is NiPdAu.
13. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
14. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
15. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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12
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
CAV25010/D
12 Page | ||
Seiten | Gesamt 12 Seiten | |
PDF Download | [ CAV25010 Schematic.PDF ] |
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