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Teilenummer | CAV25640 |
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Beschreibung | 64-Kb SPI Serial CMOS EEPROM | |
Hersteller | ON Semiconductor | |
Logo | ||
Gesamt 14 Seiten CAV25640
64-Kb SPI Serial CMOS
EEPROM
Description
The CAV25640 is a 64−Kb Serial CMOS EEPROM device
internally organized as 8Kx8 bits. This features a 64−byte page write
buffer and supports the Serial Peripheral Interface (SPI) protocol. The
device is enabled through a Chip Select (CS) input. In addition, the
required bus signals are clock input (SCK), data input (SI) and data
output (SO) lines. The HOLD input may be used to pause any serial
communication with the CAV25640 device. The device features
software and hardware write protection, including partial as well as
full array protection.
Features
• Automotive Temperature Grade 1 (−40°C to +125°C)
• 10 MHz SPI Compatible
• 2.5 V to 5.5 V Supply Voltage Range
• SPI Modes (0,0) & (1,1)
• 64−byte Page Write Buffer
• Self−timed Write Cycle
• Hardware and Software Protection
• CAV Prefix for Automotive and Other Applications Requiring Site
and Change Control
• Block Write Protection
− Protect 1/4, 1/2 or Entire EEPROM Array
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• SOIC, TSSOP 8−lead and TDFN 8−pad Packages
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
VCC
SI
CS
WP
HOLD
SCK
CAV25640
SO
VSS
Figure 1. Functional Symbol
http://onsemi.com
SOIC−8
V SUFFIX
CASE 751BD
TSSOP−8
Y SUFFIX
CASE 948AL
TDFN−8
VP2 SUFFIX
CASE 511AK
PIN CONFIGURATION
CS 1
SO
VCC
HOLD
WP SCK
VSS SI
SOIC (V), TSSOP (Y), TDFN (VP2)
Pin Name
CS
SO
WP
VSS
SI
SCK
HOLD
VCC
PIN FUNCTION
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
July, 2011 − Rev. 0
1
Publication Order Number:
CAV25640/D
CAV25640
WRITE OPERATIONS
The CAV25640 device powers up into a write disable
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the CAV25640. Care must be taken to take the
CS input high after the WREN instruction, as otherwise the
Write Enable Latch will not be properly set. WREN timing
is illustrated in Figure 3. The WREN instruction must be
sent prior to any WRITE or WRSR instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
CS
SCK
SI
SO
Dashed Line = mode (1, 1)
0 0 0 00 1 10
HIGH IMPEDANCE
Figure 3. WREN Timing
CS
SCK
SI
SO
Dashed Line = mode (1, 1)
00 0 0 0 1 00
HIGH IMPEDANCE
Figure 4. WRDI Timing
http://onsemi.com
6
6 Page CAV25640
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
e
TOP VIEW
D
A2
E1 E
A
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
L1
θ
MIN
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.50
0º
NOM
0.90
3.00
6.40
4.40
0.65 BSC
1.00 REF
0.60
MAX
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.75
8º
c
q1
SIDE VIEW
A1
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
L1
END VIEW
L
http://onsemi.com
12
12 Page | ||
Seiten | Gesamt 14 Seiten | |
PDF Download | [ CAV25640 Schematic.PDF ] |
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