|
|
PDF EDW2032BBBG Data sheet ( Hoja de datos )
| Número de pieza | EDW2032BBBG | |
| Descripción | GDDR5 SGRAM | |
| Fabricantes | Micron | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de EDW2032BBBG (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
|
No Preview Available !
2Gb: x16, x32 GDDR5 SGRAM
Features
GDDR5 SGRAM
EDW2032BBBG – 4 Meg x 32 I/O x 16 banks, 8 Meg x 16 I/O x 16 banks
Features
• VDD = VDDQ = 1.6V/1.5V ±3% and 1.35V ±3%
• Data rate: 5.0 Gb/s, 6.0 Gb/s, 7.0 Gb/s (MAX)
• 16 internal banks
• Four bank groups for tCCDL = 3 tCK
• 8n-bit prefetch architecture: 256-bit per array read
or write access for x32; 128-bit for x16
• Burst length (BL): 8 only
• Programmable CAS latency: 6–22
• Programmable WRITE latency: 3–7
• Programmable CRC READ latency: 1–3
• Programmable CRC WRITE latency: 8–14
• Programmable EDC hold pattern for CDR
• Precharge: Auto option for each burst access
• Auto refresh and self refresh modes
• Refresh cycles: 16,384 cycles/32ms
• Interface: Pseudo open drain (POD-15) compatible
outputs: 40Ω pull-down, 60Ω pull-up
• On-die termination (ODT): 60Ω or 120Ω (NOM)
• ODT and output driver strength auto calibration
with external resistor ZQ pin: 120Ω
• Programmable termination and driver strength off-
sets
• Selectable external or internal VREF for data inputs;
programmable offsets for internal VREF
• Separate external VREF for address/command in-
puts
• TC = 0°C to +95°C
• x32/x16 mode configuration set at power-up with
EDC pin
• Single-ended interface for data, address, and com-
mand
• Quarter data rate differential clock inputs CK_t,
CK_c for address and commands
• Two half data rate differential clock inputs, WCK_t
and WCK_c, each associated with two data bytes
(DQ, DBI_n, EDC)
• DDR data (WCK) and addressing (CK)
• SDR command (CK)
• Write data mask function via address bus (single/
double byte mask)
• Data bus inversion (DBI) and address bus inversion
(ABI)
• Input/output PLL on/off mode
• Duty cycle corrector (DCC) for data clock (WCK)
• Address training: Address input monitoring via DQ
pins
• WCK2CK clock training: Phase information via EDC
pins
• Data read and write training via read FIFO (FIFO
depth = 6)
• Read FIFO pattern preloaded by LDFF command
• Direct write data load to read FIFO by WRTR com-
mand
• Consecutive read of read FIFO by RDTR command
• Read/write data transmission integrity secured by
cyclic redundancy check (CRC-8)
• Read/write EDC on/off mode
• Low power modes
• RDQS mode on EDC pin
• On-die temperature sensor with readout
• Automatic temperature sensor controlled self
refresh rate
• Digital RAS lockout
• Vendor ID, FIFO depth and density info fields for
identification
• Mirror function with MF pin
• Boundary scan function with SEN pin
Options1
• Organization
– Density
– 64 Meg x 32 (words x bits)
• FBGA package
– 170-ball (12mm x 14mm)
• Package environment code
– Lead- and halogen-free
(RoHS-compliant)
• Package media
– Dry pack (tray)
– Reel
• Timing – Cycle time
– 5.0 Gb/s, 4.0 Gb/s
– 6.0 Gb/s, 5.0 Gb/s
– 7.0 Gb/s, 5.5 Gb/s
• Operating temperature
– Commercial (0°C ≤ TC ≤ +95°C)
• Revision
Marking
20
32
BG
-F
-D
-R
-50
-6A
-7A
None
B
Note:
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
PDF: 09005aef858b7e99
2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
2Gb: x16, x32 GDDR5 SGRAM
Ball Assignments and Descriptions
Table 2: 170-Ball FBGA Ball Descriptions
Symbol
A[12:0]
ABI_n
BA[3:0]
CK_t, CK_c
WCK01_t, WCK01_c/
WCK23_t, WCK23_c
CKE_n
CS_n
MF
RAS_n, CAS_n, WE_n
RESET_n
SEN
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Description
Address inputs: Provide the row address for ACTIVE commands. A[5:0] (A6) provide
the column address and A8 defines the auto precharge bit for READ/WRITE com-
mands, to select one location out of the memory array in the respective bank. A8
sampled during a PRECHARGE command determines whether the PRECHARGE ap-
plies to one bank (A8 LOW, bank selected by BA[3:0]) or all banks (A8 HIGH). The ad-
dress inputs also provide the op-code during a MODE REGISTER SET command and
the data bits during LDFF commands. A[12:8] are sampled with the rising edge of
CK_t and A[7:0] are sampled with the rising edge of CK_c.
Address bus inversion: Reduces the power requirements on address pins by limit-
ing the number of address lines driving LOW to 5. ABI_n is enabled by the corre-
sponding ABI mode register bit.
Bank address inputs: Define the bank to which an ACTIVE, READ, WRITE, or PRE-
CHARGE command is being applied. BA[3:0] define which mode register is loaded
during the MODE REGISTER SET command. BA[3:0] are sampled with the rising edge
of CK_t.
Clock: CK_t and CK_c are differential clock inputs. Command inputs are latched on
the rising edge of CK_t. Address inputs are latched on the rising edge of CK_t and
the rising edge of CK_c. All latencies are referenced to CK_t. CK_t and CK_c are ex-
ternally terminated.
Data Clocks: WCK_t and WCK_c are differential clocks used for write data capture
and read data output. WCK01_t and WCK01_c are associated with DQ[15:0], DBI0_n,
DBI1_n, EDC0, and EDC1. WCK23_t and WCK23_c are associated with DQ[31:16],
DBI2_n, DBI3_n, EDC2, and EDC3. WCK clocks operate at nominally twice the CK
clock frequency.
Clock enable: CKE_n enables (registered LOW) and disables (registered HIGH) inter-
nal circuitry and clocks on the SGRAM. The specific circuitry that is enabled/disabled
is dependent upon the device configuration and operating mode. Taking CKE_n
HIGH provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle), or active power-down (row active in any bank). CKE_n is synchronous for pow-
er-down entry and exit and for self refresh entry. CKE_n must be maintained LOW
throughout read and write accesses. Input buffers (excluding CKE_n) are disabled
during SELF REFRESH operation. The value of CKE_n latched at power-up with RE-
SET_n going HIGH determines the termination value of the address and command
inputs.
Chip select: CS_n enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS_n is registered HIGH, but in-
ternal command execution continues. CS_n is considered part of the command code.
Mirror function: VDDQ CMOS input. Must be tied to VDDQ or VSS.
Command inputs: RAS_n, CAS_n, and WE_n (along with CS_n) define the com-
mand being entered.
Reset: RESET_n is an active LOW CMOS input referenced to VSS. A full chip reset may
be performed at any time by pulling RESET_n LOW. With RESET_n LOW all ODTs are
disabled.
Scan enable: VDDQ CMOS input. Must be tied to VSS when not in use.
PDF: 09005aef858b7e99
2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet EDW2032BBBG.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| EDW2032BBBG | 2G bits GDDR5 SGRAM |  Elpida |
| EDW2032BBBG | GDDR5 SGRAM | Micron |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |