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AFE1230 Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer AFE1230
Beschreibung G.SHDSL ANALOG FRONT-END
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 15 Seiten
AFE1230 Datasheet, Funktion
AFE1230
AFE1230
SBWS015A – AUGUST 2001
G.SHDSL ANALOG FRONT-END
FEATURES
q E1, T1, AND SUBRATE OPERATION
q COMPLIES WITH G.SHDSL AND HDSL2
q 16-BIT, DELTA-SIGMA CONVERTERS
q ON-CHIP DRIVER AND PGA
q PROGRAMMABLE tx AND rx FILTERS
q SERIAL DIGITAL INTERFACE
q 750mW POWER DISSIPATION AT E1
q +5V POWER (5V OR 3.3V DIGITAL)
q SSOP-28 PACKAGE
q –40°C TO +85°C TEMPERATURE RANGE
DESCRIPTION
Texas Instrument’s analog front-end chip, the AFE1230, is
designed to greatly reduce the size and cost of G.SHDSL
and HDSL2 application designs. It provides a transceiver as
the line interface between the Digital Signal Processor
(DSP) and the local loop. The AFE1230 is designed to
handle upstream and downstream data transmission over a
wide range of data rates from 64kbps to 2.5Mbps. Function-
ally, this unit consists of a transmitter and receiver section.
The transmitter section consists of a digital interpolation
filter, a 16-bit, delta-sigma Digital-to-Analog (D/A) con-
verter, a digitally programmable fifth-order or seventh-order
SC (Switched Capacitor) low-pass filter, and a differential
output line driver. The receiver section includes an input
Programmable Gain Amplifier (PGA), a 16-bit, delta-sigma
Analog-to-Digital (A/D) converter, and a programmable
decimation filter.
The AFE1230 receives a 16-bit data word plus an 8-bit control
byte via the serial interface to facilitate the D/A conversion
and control functions. The subsequent analog signal is sent to
the on-chip line driver that provides 14.5dBm power into a
135line for G.SHDSL operation. In addition, the on-chip
line driver can be used as an output buffer with an external line
driver, such as the OPA2677, to generate over 17dBm power
into a 135line for HDSL2 operation. With an appropriate
DSP, the transmitted Power Spectral Density (PSD) complies
with either the G.SHDSL standard or with the HDSL2 stan-
dard (via an OPA2677 used as an external driver).
In the receive path, the input amplifier sums the signals from
the line and hybrid path to perform first-order analog echo
cancellation. The resultant signal is then digitized by the rest
of the receive section into a 16-bit digital word that is sent to
the external DSP.
This IC operates on a single 5V supply, while the digital supply
can be from 3.3V to 5V. It is housed in a SSOP-28 package.
The typical power consumption is 750mW at E1 rates with
G.SHDSL (560mW for HDSL2 operation) and an operation
temperature range of –40°C to +85°C.
Digital
Interpolation
LPF
∆Σ 16-Bit
D/A Converter
Programmable
SC
LPF
Driver/
Buffer
txLINE
txLINE
MCLK
txBaud
txData
rxBaud
rxData
tx and rx
Digital
Interface
Registers
Programmable
Digital
LPF
∆Σ 16-Bit
A/D Converter
PGA
Input
Amplifier
hybINPUT
hybINPUT
rxINPUT
rxINPUT
AFE1230
Patents Pending
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright © 2001, Texas Instruments Incorporated






AFE1230 Datasheet, Funktion
Receive Amplifier
The AFE1230 receive channel includes an input amplifier
with a differential summer junction on-chip for echo cancel-
lation, as shown in Figure 4. Four external resistors are
needed with 10kas the required value for each receiver-
input pair as well as 20kfor each hybrid-input pair. The
common-mode voltage of the receive amplifier is AVDD/2
(typical value is 2.5V).
Serial Digital Interface Operation
The AFE1230 digital interface uses a five-line serial interface,
signal names are: Master Clock (MCLK), Transmit Baud
Clock (txBaud), Transmit Data (txData), Receive Baud Clock
(rxBaud), and Receive Data (rxData). MCLK, txBaud, rxBaud,
and txData must come from the external DSP where data is
transmitted in synchronization with MCLK. MCLK is used as
the internal master clock to the AFE1230 and can run up to
40.8MHz. txBaud and rxBaud must be the same frequency
and synchronous with MCLK, however, the phase of these
signals may be different. Each baud period contains 48
MCLK cycles. During each baud cycle, txData will contain
two 16-bit transmit words with two control bytes. Each bit is
latched internally to the AFE at the rising edge of MCLK.
Figures 5, 6, and 7 illustrate the bit designations as well as the
proper timings required to operate the AFE1230.
MCLK: The master clock of AFE1230 for both transmit
and receive sections, generated by the DSP. It runs at 48x the
symbol rate and can be varied from 1.28MHz to 40.8MHz
(37.12MHz for E1). MCLK must use a 50/50 duty cycle.
txBaud: The transmit data baud clock, generated by the
DSP. txBaud is 517.33kHz for T1 and 773.33kHz for E1
(2.3Mbps). It may vary from 26.7kHz to 850kHz. A txBaud
period consists of 48 periods of the MCLK. The time (tW) of
the txBaud should not be smaller than one MCLK period.
Within the period of 48 MCLK clocks, the rising edge of the
txBaud can occur any time except in the period of tF, and the
falling edge of txBaud can occur at any time of the tF period.
txData: The input digital data of AFE1230. This signal comes
from an external DSP with 48 bits per baud period. The 48 bits
include two 16-bit words of D/A converter input data and two
8-bit control bytes (see Tables IV and V). The D/A converter
is updated two times per symbol period and data is latched by
the AFE1230 on the rising edge of MCLK. txData must be
stable at least 2.5ns before the rising edge of MCLK and it must
remain stable at least 2.5ns after the rising edge of MCLK.
rxBaud: The receive data baud clock, generated by the DSP.
rxBaud is 517.33kHz for T1 and 773.33kHz for E1 (2.3Mbps).
It may vary from 26.7kHz to 850kHz. One rxBaud period
consists of 48 periods of the MCLK. Within the period of 48
MCLK clocks, the rising edge of the rxBaud can occur at any
time except in tF period, and the falling edge of rxBaud can
occur at any time during tF. The width of the rxBaud pulse
should be no shorter than one period of MCLK.
rxData: The output digital data of AFE1230, sent to the
external DSP with 48 bits per baud period. The 48 bits include
two 16-bit words of receive data and two 8-bit control words
(Reserved) (see Tables VI and VII). The A/D converter is
updated two times per symbol period and rxData is changed
by AFE1230 at the falling edge of MCLK. rxData is stable at
least 2.5ns before the rising edge of MCLK and it remains
stable at least 2.5ns after the rising edge of MCLK.
R3
R4
Vhy R5
Vrx R6
hy+
rx+
hy
rx
External Circuit
R3 = R5 = 20k
R4 = R6 = 10k
FIGURE 4. Internal Receive Amplifier.
RF
Internal
Amp
Vp-p 6.2V
∆Σ
A/D Converter
RF
6 AFE1230
SBWS015A

6 Page









AFE1230 pdf, datenblatt
AFE1230
txLINE+
txLINE
rxHYBp
rxHYBm
rxLINE+
rxLINE
+12V
499
0.1µF 49.9
1k
0.1µF
49.9
1µF
OPA2677-a
1.2nF
2k
2k
453
453
0.11µF
R
453
17.3Vp-p
OPA2677-b
1µF
R1
10.9
R2
10.9
22nF 1:2.3
Zi
22nF
0.47µF
135
3.3pF(1)
10pF(1)
3.3pF(1)
10pF(1)
R3
10k
R5
10k
R4
10k
R6
10k
499
Compromise
Network
0.1µF
0.1µF
0.1µF
0.1µF
Overload
Protection
NOTE: (1) These components provide low-pass filtering and are optional, since the AFE1230 provides an internal low-pass
filter with 1MHz cutoff frequency on the front end of the receiver, as well as oversampling by the A/D converter.
FIGURE 10. AFE1230 Line Interface with OPA2677 for HDSL2.
LAYOUT
The AFE1230 has two conflicting requirements: it must
accept and deliver high-speed digital signals and it must
generate, drive, and convert precision analog signals. To
achieve optimal system performance with the AFE1230,
both the digital and the analog sections must be treated
carefully in board layout design. The power supply for the
digital section of AFE1230 can range from 3.3V to 5V. This
supply should be decoupled to digital grounds with ceramic
0.1µF capacitors placed as close to the GNDD and DVDD
pins as possible. DVDD may be supplied by a wide-printed
circuit board trace. A digital ground plane underneath all
digital pins is strongly recommended. All GNDA pins should
be connected directly to a common analog ground plane and
all the AVDD pins should be connected to an analog 5V
power plane. Both of these planes should have a low imped-
ance path to power supply. The analog power-supply pins
should be decoupled to analog grounds with ceramic 0.1µF
capacitors placed as close to the AFE1230 as possible. One
10µF tantalum capacitor should be used between the analog
supply and analog ground. Ideally, all ground planes and
traces and all power planes and traces should return to the
power connector before being connected together (if neces-
sary). Each ground and power pair should be routed over
each other, and should not overlay any portion of another
pair, and the pairs should be separated by a distance of 0.25
inches (6mm) at least. One exception is that the digital and
analog ground planes should be connected together under-
neath the AFE1230 by a small trace.
12 AFE1230
SBWS015A

12 Page





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