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PC3030K Schematic ( PDF Datasheet ) - Pixelplus

Teilenummer PC3030K
Beschreibung 1/3.7 inch NTSC/PAL CMOS Image Sensor
Hersteller Pixelplus
Logo Pixelplus Logo 




Gesamt 30 Seiten
PC3030K Datasheet, Funktion
Preliminary
Data sheet
1/3.7 inch NTSC/PAL CMOS Image Sensor with
640 X 480 Pixel Array
PC3030K
Rev 0.5
Last update : 27. Apr. 2011
6th Floor, Gyeonggi R&DB Center, 906-5 Iui-dong, Yeongtong-gu,
Suwon-si, Gyeonggi-do, 443-766, Korea
Tel : 82-31-888-5300, FAX : 82-31-888-5398
Copyright 2011, Pixelplus Co.,Ltd
ALL RIGHTS RESERVED






PC3030K Datasheet, Funktion
PRELIMINARY
PC3030K
1/3.7 inch NTSC/PAL CMOS Image Sensor with
640 X 480 Pixel Array
PIN Descriptions
Num NAME I/O Type
PAD Description
1 AVDD1 P Analog VDD1 :2.8V DC.
2 AGND1 P Analog Ground1
3 CN
4 CP
5 CVDD
O
Composite Differential Negative signal
(75 ohm single termination(LCD), 37.5 ohm double termination (CRT))
O
Composite Differential Positive signal.
(75 ohm single termination(LCD), 37.5 ohm double termination (CRT))
P DAC power supply : 2.8V DC
6 CGND
P DAC power ground
7 REXT
I
External Resistor. The resistor value can be changed by user tuning. (Typically 30k ohm
when CN/CP 37.5 ohm termination, 60k ohm when CN/CP 75 ohm termination)
8 D0
I/O Mirror Strap Input bit 0 / Digital Output bit 0, Motion detection signal out
9 PCLK
10 DVDD
11 HVDD
O
Pixel clock. Data can be latched by external devices at the rising or falling edge of PCLK.
The polarity can be controlled anyway.
Digital Power supply : In case of using on-chip digital regulator, DVDD must
P be tied to DGND by total 1uF bypass capacitor. Otherwise, 1.5V DC must be
supplied with 100nF to DGND.
P Digital VDD for I/O : 3.3V. Voltage range for all output signals is (0V or HVDD)
12 HGND
P Digital GND for I/O
13 DGND
P Digital GND for core
14 X1
I Crystal input pad or Master clock input pad
15 X2
O Crystal output pad *(1)
16 D1
I/O Mirror Strap Input bit 1 / Digital Output bit 1
17 CSB
O Chip Select Signal for Serial Peripheral Interface(SPI)
18 MOSI
O Data Output for Serial Peripheral Interface(SPI)
19 MISO
I Data Input Signal for Serial Peripheral Interface(SPI)
20 SCK
O Clock Signal for Serial Peripheral Interface(SPI)
(1) In case of using External clock, crystal output pad(X2) must be floated and clock input PAD is X1.
Rev 0.6
[Table 2] Pin Descriptions (continue)
6/122
CrystalImage & ImagingInnovation

6 Page









PC3030K pdf, datenblatt
PRELIMINARY
PC3030K
1/3.7 inch NTSC/PAL CMOS Image Sensor with
640 X 480 Pixel Array
[Fig. 7] shows the bayer data sequence of PC3030K. The def ault sequence Bayer data is [RGRG…] f or
even rows and [GBGB…] f or odd rows.
VSYNC
HSYNC
VSYNC period = frameheight + 1 [line]
VSYNC positive width = vsyncstoprow vsyncstartrow [line]
HSYNC period = framewidth + 1 [PCLK]
HSYNC positive width = windowx2 windowx1 +1 [PCLK]
HSYNC
X1
PCLK
DATA(e) AB R G R
DATA(o) AB G B G
G R G FF
B G B FF
[Fig. 7] Timing Diagram f or VSYNC, HSYNC, X1, PCLK and Data ( Bayer mode )
AB R
AB G
Rev 0.6
12/122
CrystalImage & ImagingInnovation

12 Page





SeitenGesamt 30 Seiten
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