Data Sheet
600 mA, Ultralow Noise,
High PSRR, RF Linear Regulator
ADM7155
FEATURES
Input voltage range: 2.3 V to 5.5 V
Output voltage range: 1.2 V to 3.4 V
Maximum load current: 600 mA
Low noise
0.9 µV rms total integrated noise from 100 Hz to 100 kHz
1.6 µV rms total integrated noise from 10 Hz to 100 kHz
Noise spectral density: 1.5 nV/√Hz from 10 kHz to 1 MHz
PSRR: >90 dB from 200 Hz to 200 kHz; 57 dB at 1 MHz
Dropout voltage: 120 mV typical at VOUT = 3.3 V, IOUT = 600 mA
Initial accuracy: ±0.5%
Accuracy over line, load, and temperature: −2.0% (minimum),
+1.5% (maximum)
Quiescent current, IGND = 4 mA at no load
Low shutdown current: 0.2 μA
Stable with a 10 µF ceramic output capacitor
8-lead LFCSP and 8-lead SOIC packages
Precision enable
Supported by ADIsimPower tool
APPLICATIONS
Regulation to noise sensitive applications: PLLs, VCOs, and
PLLs with integrated VCOs
Communications and infrastructure
Backhaul and microwave links
GENERAL DESCRIPTION
The ADM7155 is an adjustable linear regulator that operates
from 2.3 V to 5.5 V and provides up to 600 mA of load current.
Output voltages from 1.2 V to 3.4 V are possible depending on
the model. Using an advanced proprietary architecture, it
provides high power supply rejection and ultralow noise,
achieving excellent line and load transient response with only a
10 µF ceramic output capacitor.
The ADM7155 is available in four models that optimize power
dissipation and PSRR performance as a function of input and
output voltage. See Table 9 and Table 10 for selection guides.
The ADM7155 regulator typical output noise is 0.9 μV rms from
100 Hz to 100 kHz for fixed output voltage options and 1.5 nV/√Hz
for noise spectral density from 10 kHz to 1 MHz. The ADM7155
is available in 8-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC
packages, making it not only a very compact solution but also
providing excellent thermal performance for applications requiring
up to 600 mA of load current in a small, low profile footprint.
Rev. A
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TYPICAL APPLICATION CIRCUIT
VIN = 3.5V
CIN
10µF
ON
OFF
ADM7155
VIN VOUT
EN REF
CBYP
1µF
VBYP
BYP
REF_SENSE
CREG
10µF
VREG
VREG
GND
VOUT = 3.0V
COUT
10µF
REF = 1.2V
CREF
R1 1µF
VOUT = 1.2V × (R1 + R2)/R2
R2
1kΩ < R2 < 200kΩ
Figure 1. Regulated 3.0 V Output from 3.5 V Input
10k
NOISE FLOOR
1.0µF
3.3µF
1k 10µF
33µF
100µF
330µF
100 1000µF
10
1
0.1
0.1 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 2. Noise Spectral Density for Different Values of CBYP
Table 1. Related Devices
Model
Input
Voltage
ADM7150ACP 4.5 V to 16 V
ADM7150ARD 4.5 V to 16 V
ADM7151ACP 4.5 V to 16 V
ADM7151ARD 4.5 V to 16 V
ADM7154ACP 2.3 V to 5.5 V
ADM7154ARD 2.3 V to 5.5 V
Output
Current
800 mA
800 mA
800 mA
800 mA
600 mA
600 mA
Fixed/
Adj1
Fixed
Fixed
Adj
Adj
Fixed
Fixed
Package
8-Lead LFCSP
8-Lead SOIC
8-Lead LFCSP
8-Lead SOIC
8-Lead LFCSP
8-Lead SOIC
1 Adj means adjustable.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
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Technical Support
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ADM7155
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VREG 1
8 VIN
VOUT 2
BYP 3
GND 4
ADM7155
TOP VIEW
(Not to Scale)
7 EN
6 REF
5 REF_SENSE
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
THE PACKAGE. THE EXPOSED PAD ENHANCES
THERMAL PERFORMANCE, AND IT IS ELECTRICALLY
CONNECTED TO GND INSIDE THE PACKAGE. CONNECT
THE EP TO THE GROUND PLANE ON THE BOARD TO
ENSURE PROPER OPERATION.
Figure 3. 8-Lead LFCSP Pin Configuration
VREG 1
8 VIN
VOUT 2 ADM7155 7 EN
TOP VIEW
BYP 3 (Not to Scale) 6 REF
GND 4
5 REF_SENSE
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
THE PACKAGE. THE EXPOSED PAD ENHANCES
THERMAL PERFORMANCE, AND IT IS ELECTRICALLY
CONNECTED TO GND INSIDE THE PACKAGE. CONNECT
THE EP TO THE GROUND PLANE ON THE BOARD TO
ENSURE PROPER OPERATION.
Figure 4. 8-Lead SOIC Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VREG
Regulated Input Supply Voltage to LDO Amplifier. Bypass VREG to GND with a 10 μF or greater
capacitor.
2
VOUT
Regulated Output Voltage. Bypass VOUT to GND with a 10 μF or greater capacitor.
3 BYP Low Noise Bypass Capacitor. Connect a 1 μF capacitor from the BYP pin to GND to reduce noise. Do not
connect a load to ground.
4 GND Ground Connection.
5
REF_SENSE
Reference Sense. Connect Pin 5 to the REF pin. Do not connect Pin 5 to VOUT or GND.
6 REF Low Noise Reference Voltage Output. Bypass REF to GND with a 1 μF capacitor. Short REF_SENSE to REF
for fixed output voltages. Do not connect a load to ground.
7 EN Enable. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic
startup, connect EN to VIN.
8 VIN Regulator Input Supply Voltage. Bypass VIN to GND with a 10 μF or greater capacitor.
EP Exposed Pad. The exposed pad is located on the bottom of the package. The exposed pad enhances
thermal performance, and it is electrically connected to GND inside the package. Connect the EP to the
ground plane on the board to ensure proper operation.
Rev. A | Page 6 of 24

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ADM7155
T
1
2
CH1 200mA Ω BW CH2 5mV BW M4.0µs A CH1 212mA
T 10.2%
Figure 35. Load Transient Response, ILOAD = 10 mA to 510 mA,
VOUT = 3.3 V, VIN = 3.8 V, CH1 = IOUT, CH2 = VOUT
T
1
2
CH1 200mA Ω BW CH2 5mV BW M4.0µs A CH1 212mA
T 10.2%
Figure 36. Load Transient Response, ILOAD = 100 mA to 600 mA,
VOUT = 3.3 V, VIN = 3.8 V, CH1 = IOUT, CH2 = VOUT
T
1
2
CH1 200mA Ω BW CH2 5mV BW M4.0µs A CH1 204mA
T 10.4%
Figure 37. Load Transient Response, ILOAD = 10 mA to 510 mA,
VOUT = 1.8 V, VIN = 2.3 V, CH1 = IOUT, CH2 = VOUT
T
1
2
Data Sheet
CH1 200mA Ω BW CH2 5mV BW M4µs A CH1 532mA
T 10.6%
Figure 38. Load Transient Response, ILOAD = 100 mA to 600 mA,
VOUT = 1.8 V, VIN = 2.3 V, CH1 = IOUT, CH2 = VOUT
T
2
1
CH1 1V BW CH2 1mV BW M400ns
T 10.4%
A CH1 4.38V
Figure 39. Line Transient Response, 1 V Input Step, ILOAD = 600 mA,
VOUT = 3.3 V, VIN = 3.9 V, CH1 = VIN, CH2 = VOUT
T
21
CH1 1V BW CH2 1mV BW M400ns
T 11.4%
A CH1 3.5V
Figure 40. Line Transient Response, 1 V Input Step, ILOAD = 600 mA,
VOUT = 1.8 V, VIN = 2.4 V, CH1 = VIN, CH2 = VOUT
Rev. A | Page 12 of 24

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