PDF CAT34TS04 Data sheet ( Hoja de datos )

Número de pieza	CAT34TS04
Descripción	Digital Output Temperature Sensor
Fabricantes	ON Semiconductor
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No Preview Available ! CAT34TS04 Digital Output Temperature Sensor with On-board SPD EEPROM Description The CAT34TS04 is a combination Temperature Sensor (TS) and 4−Kb of Serial Presence Detect (SPD) EEPROM, which implements the JEDEC TSE2004av DDR4 specification and supports the Standard (100 kHz), Fast (400 kHz) and Fast Plus (1 MHz) I2C protocols. The TS measures temperature at least 10 times every second. Temperature readings can be retrieved by the host via the serial interface, and are compared to high, low and critical trigger limits stored into internal registers. Over or under limit conditions can be signaled on the open−drain EVENT pin. One of the two available 2−Kb SPD EEPROM banks (referred to as SPD pages in the TSE2004av specification) is activated for access at power−up. After power−up, banks can be switched via software command. Each of the four 1−Kb SPD EEPROM blocks can be Write Protected by software command. Features • JEDEC TSE2004av Compliant Temperature Sensor • Temperature Range: −20°C to +125°C • DDR4 DIMM Compliant SPD EEPROM • Supply Range: 1.7 V − 5.5 V (SPD EEPROM) and 2.2 V − 5.5 V (TS) • I2C / SMBus Interface • Schmitt Triggers and Noise Suppression Filters on SCL and SDA Inputs • 16−Byte Page Write Buffer • Low Power CMOS Technology • 2 x 3 x 0.75 mm TDFN Package and 2 x 3 x 0.5 mm UDFN Package • These Devices are Pb−Free and are RoHS Compliant VCC SCL A2, A1, A0 SDA CAT34TS04 EVENT VSS Figure 1. Functional Symbol http://onsemi.com TDFN−8 VP2 SUFFIX CASE 511AK UDFN−8 HU4 SUFFIX CASE 517AZ PIN CONFIGURATION A0 1 A1 A2 (Top View) VSS VCC EVENT SCL SDA TDFN (VP2), UDFN (HU4) For the location of Pin 1, please consult the corresponding package drawing. MARKING DIAGRAM TDFN−8 4TA ALL YM G 4UA ALL YM UDFN−8 G 4TA, 4UA = Specific Device Code A = Assembly Location Code LL = Assembly Lot Number (Last Two Digits) Y = Production Year (Last Digit) M = Production Month (1 − 9, O, N, D) G = Pb−Free Package = Pin 1 Indicator PIN FUNCTIONS Pin Name A0, A1, A2 SDA SCL EVENT VCC VSS DAP Function Device Address Input Serial Data Input/Output Serial Clock Input Open−drain Event Output Power Supply Ground Backside Exposed DAP at VSS ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 18 of this data sheet. © Semiconductor Components Industries, LLC, 2013 October, 2013 − Rev. 6 1 Publication Order Number: CAT34TS04/D 1 page SCL FROM MASTER CAT34TS04 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START Figure 4. Acknowledge Timing ACKNOWLEDGE SCL 70% tSU:STA SDA IN tF tLOW 7300%% tHD:STA 7300%% SDA OUT tHIGH tR 70% 30% tHD:DAT 70% tSU:DAT 30% tDH 70% 30% Figure 5. Bus Timing 70% 30% tSU:STO 70% 70% tBUF Table 7. COMMAND SET (Notes 9, 10) Function Specific Preamble Select Address R/W_n A0 Pin Function Read Temperature Registers Abbr RTR b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 1 LSA2 LSA1 LSA0 1 0 or 1 Write Temperature Registers WTR 0 Read EE Memory RSPD 1 0 1 0 LSA2 LSA1 LSA0 1 0 or 1 Write EE Memory WSPD 0 Set Write Protection, block 0 SWP0 0 1 1 0 0 0 1 0 VHV Set Write Protection, block 1 SWP1 1000 VHV Set Write Protection, block 2 SWP2 1010 VHV Set Write Protection, block 3 SWP3 0000 VHV Clear All Write Protection CWP 0110 VHV Read Protection Status, block 0 RPS0 0 0 1 1 0, 1 or VHV Read Protection Status, block 1 RPS1 1 0 0 1 0, 1 or VHV Read Protection Status, block 2 RPS2 1 0 1 1 0, 1 or VHV Read Protection Status, block 3 RPS3 0 0 0 1 0, 1 or VHV Set SPD Page Address to 0 (Select Lower Bank) SPA0 1 1 0 0 0, 1 or VHV Set SPD Page Address to 1 (Select Upper Bank) SPA1 1 1 1 0 0, 1 or VHV Read SPD Page Address RPA 1 1 0 1 0, 1 or VHV Reserved − All Other Encodings 9. LSAx stands for Logic State of Address pin x. 10. If VHV is not applied on the A0 pin during SWP/CWP commands, the CAT34TS04 will respond with NoACK after the 3rd byte and will not execute the SWP/CWP instruction. During RPS/SPA/RPA commands the state of pin A0 must be stable for the duration of the sequence. http://onsemi.com 5 5 Page CAT34TS04 Table 10. THE TS REGISTERS Register Address Register Name 0x00 Capability Register 0x01 Configuration Register 0x02 High Limit Register 0x03 Low Limit Register 0x04 Critical Limit Register 0x05 Temperature Data Register 0x06 Manufacturer ID Register 0x07 Device ID/Revision Register Power−On Default 0x007F 0x0000 0x0000 0x0000 0x0000 Undefined 0x1B09 0x2200 Read/Write Read Read/Write Read/Write Read/Write Read/Write Read Read Read Table 11. CAPABILITY REGISTER B15 B14 B13 RFU (Note 16) RFU RFU B7 B6 B5 EVSD TMOUT VHV 16. RFU stands for Reserved for Future Use B12 RFU B11 RFU B4 B3 TRES [1:0] B10 RFU B2 RANGE B9 RFU B1 ACC B8 RFU B0 EVENT Bit Description B15:B8 Reserved for future use; can not be written; should be ignored; will read as 0 B7 (Note 17) 0: Configuration Register bit 4 is frozen upon Configuration Register bit 8 being set (i.e. a TS shut−down freezes the EVENT output) 1: Configuration Register bit 4 is cleared upon Configuration Register bit 8 being set (i.e. a TS shut−down de−asserts the EVENT output) B6 0: Not used 1: The TS implements SMBus time−out within the range 25 to 35 ms B5 B4:B3 0: Not used 1: Defined for compatibility with CAT34TS02 device (VHV is supported) 00: LSB = 0.50°C (9 bit resolution) 01: LSB = 0.25°C (10 bit) 10: LSB = 0.125°C (11 bit) 11: LSB = 0.0625°C (12 bit) B2 0: Not used 1: The temperature monitor can read temperatures below 0°C and sets the sign bit appropriately B1 0: Not used 1: The temperature monitor has ±1°C accuracy over the active range (75°C to 95°C) and ±2°C accuracy over the monitoring range (40°C to 125°C) B0 0: Not used 1: The device supports interrupt capabilities 17. Configuration Register bit 4 can be cleared (but not set) after Configuration Register bit 8 is set, by writing a “1” to Configuration Register bit 5 (EVENT output can be de−asserted during TS shut−down periods) http://onsemi.com 11 11 Page

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