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Teilenummer | CAT93C46B |
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Beschreibung | 1Kb Microwire Serial EEPROM | |
Hersteller | ON Semiconductor | |
Logo | ||
Gesamt 14 Seiten CAT93C46B
1-Kb Microwire Serial
EEPROM
Description
The CAT93C46B is a 1−Kb Serial EEPROM memory device which
is configured as either 64 registers of 16 bits (ORG pin at VCC) or 128
registers of 8 bits (ORG pin at GND). Each register can be written (or
read) serially by using the DI (or DO) pin. The CAT93C46B features a
self−timed internal write with auto−clear. On−chip Power−On Reset
circuit protects the internal logic against powering up in the wrong
state.
Features
• High Speed Operation: 4 MHz
• 1.8 V (1.65 V*) to 5.5 V Supply Voltage Range
• Selectable x8 or x16 Memory Organization
• Self−Timed Write Cycle with Auto−Clear
• Sequential Read
• Software Write Protection
• Power−up Inadvertant Write Protection
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial and Extended Temperature Ranges
• 8−pin PDIP, SOIC, TSSOP and 8−pad UDFN and TDFN Packages
• This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant†
VCC
ORG
CS
SK
DI
CAT93C46B
DO
GND
Figure 1. Functional Symbol
*CAT93C46Bxx−xxL (TA = −205C to +855C)
†For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
SOIC−8
V, W** SUFFIX
CASE 751BD
SOIC−8
X SUFFIX
CASE 751BE
UDFN−8
HU4 SUFFIX
CASE 517AZ
TDFN−8**
VP2 SUFFIX
CASE 511AK
PIN CONFIGURATIONS
CS 1
SK
DI
DO
VCC
NC
ORG
GND
NC
VCC
CS
SK
1
ORG
GND
DO
DI
PDIP (L), SOIC (V, X),
TSSOP (Y), UDFN (HU4),
TDFN (VP2)**
(Top View)
SOIC (W)**
(Top View)
** Not recommended for new designs.
PIN FUNCTION
Pin Name
Function
CS Chip Select
SK Clock Input
DI Serial Data Input
DO Serial Data Output
VCC
GND
Power Supply
Ground
ORG
Memory Organization
NC No Connection
Note: When the ORG pin is connected to VCC, the
x16 organization is selected. When it is connected
to ground, the x8 organization is selected. If the
ORG pin is left unconnected, then an internal pullup
device will select the x16 organization.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
January, 2014 − Rev. 3
1
Publication Order Number:
CAT93C46B/D
CAT93C46B
Write
After receiving a WRITE command (Figure 5), address
and the data, the CS (Chip Select) pin must be deselected for
a minimum of tCSMIN. The falling edge of CS will start the
self clocking for auto−clear and data store cycles on the
memory location specified in the instruction. The clocking
of the SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C46B can be determined by selecting the device and
polling the DO pin. Since this device features Auto−Clear
before write, it is NOT necessary to erase a memory location
before it is written into.
Erase
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be de−asserted for a minimum of
tCSMIN (Figure 6). The falling edge of CS will start the self
clocking clear cycle of the selected memory location. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C46B can be determined by selecting the device and
polling the DO pin. Once cleared, the content of a cleared
location returns to a logical “1” state.
Erase All
Upon receiving an ERAL command (Figure 7), the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C46B can be determined by selecting the device and
polling the DO pin. Once cleared, the contents of all memory
bits return to a logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN (Figure 8). The falling edge of CS will start the self
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy status of
the CAT93C46B can be determined by selecting the device
and polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
SK
tCSMIN
CS
AN AN−1
DI 1 0 1
A0 DN
D0
STATUS
VERIFY
STANDBY
tSV tHZ
HIGH−Z
DO
READY
HIGH−Z
BUSY
tEW
Figure 5. Write Instruction Timing
http://onsemi.com
6
6 Page D
E
PIN #1 INDEX AREA
TOP VIEW
CAT93C46B
PACKAGE DIMENSIONS
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ−01
ISSUE O
Ab
e
L
DAP SIZE 1.8 x 1.8
E2
PIN #1
IDENTIFICATION
A1
SIDE VIEW
D2
BOTTOM VIEW
SYMBOL
A
A1
A3
b
D
D2
E
E2
e
L
MIN
NOM
MAX
0.45 0.50 0.55
0.00 0.02 0.05
0.127 REF
0.20 0.25 0.30
1.95 2.00 2.05
1.35 1.40 1.45
2.95 3.00 3.05
1.25 1.30 1.35
0.50 REF
0.25 0.30 0.35
Notes:
(1) All dimensions are in millimeters.
(2) Refer JEDEC MO-236/MO-252.
0.065 REF
DETAIL A A3 A
FRONT VIEW
A3 0.0 - 0.05
0.065 REF
Copper Exposed
DETAIL A
http://onsemi.com
12
12 Page | ||
Seiten | Gesamt 14 Seiten | |
PDF Download | [ CAT93C46B Schematic.PDF ] |
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